Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs

  • B. Chagun Basha
  • Stanisław J. Piestrak
  • Sébastien Pillement
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)


SRAM-based FPGAs have been employed extensively in many applications to implement adaptable systems whose functionalities can be changed at runtime. Unfortunately, even in terrestrial applications the SRAM configuration memory of FPGA devices is highly susceptible to radiation which may cause not only single but also multiple errors in physically adjacent memory cells, called Multiple Bit Upsets (MBUs). This paper proposes a new built-in 3-Dimensional Hamming (3DH) error correcting scheme to mitigate MBUs. The estimations of the probability of occurrence of undetected multiple errors indicate significant improvement of the error correction capabilities of the 3DH scheme proposed here, compared to known 2DH and 1DH schemes. The other important advantage of the new scheme is that it can provide faster reconfiguration of configuration frames affected by multiple errors, because error correction can be done using an internal bus alone.


Data Frame Error Pattern Soft Error Cyclic Redundancy Check FPGA Device 
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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • B. Chagun Basha
    • 1
  • Stanisław J. Piestrak
    • 2
  • Sébastien Pillement
    • 3
  1. 1.IETRUniversité de Rennes 1France
  2. 2.IJLUniversité de LorraineFrance
  3. 3.IETR, Polytech’NantesLUNAM UniversitéFrance

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