Advertisement

An Efficient Implementation of the Adams-Hamilton’s Demosaicing Algorithm in FPGAs

  • Jalal Khalifat
  • Ali Ebrahim
  • Tughrul Arslan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8405)

Abstract

Demosaicing is the process of reconstructing a full color image from incomplete samples generated by typical image sensors. This paper discusses the Adams-Hamilton’s demosaicing algorithm and presents a high-performance and cost-effective implementation of the algorithm in Field Programmable Gate Arrays (FPGAs). The paper also presents a proposed demosaicing hardware architecture which increases the number of pixels processed in a single clock cycle by using efficient pipelining. Images obtained from our FPGA implementation are compared to images obtained from standard software demosaicing functions. Our proposed hardware architecture is shown to outperform previous hardware implementations of the algorithm. Our architecture is capable of processing up to 419 MPixels/s.

Keywords

Adams-Hamilton FPGAs Demosaicing PSNR HD Bayer CFA 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bayer, B.E.: Color imaging array. U.S. Patent No. 3,971,065 (July 1976)Google Scholar
  2. 2.
    Freeman, W.T.: Median filter for reconstruction missing color samples. U.S. Patent No. 4,724,395 (1988)Google Scholar
  3. 3.
    Hamilton, J.F., Adams, J.E.: Adaptive Color Plane Interpolation in Single Sensor Color Electronic Camera. U.S. Patent, No. 5629734 (1997)Google Scholar
  4. 4.
    Nguyen, T.: System and method for asymmetrically demosaicing raw data images using color discontinuity equalization. U.S. Patent No. 0,167,602 A1 (2002)Google Scholar
  5. 5.
    Fuentes, I.O.H., Bravo-Zanoguera, M.E., Yanez, G.G.: FPGA Implementation of the Bilinar Interpolation Algorithm for Image Demosaicking. In: International Conference on Electrical, Communications, and Computers (CONIELECOM), pp. 25–28 (2009)Google Scholar
  6. 6.
    Jair, G.L., Miguel, A.A., Julio, W.V.: A Digital Real Time Image Demosaicking Imple-mentation for High Definition Video Cameras. In: Electronics, Robotics and Automotive Mechanics Conference (CERMA), pp. 565–569 (2008)Google Scholar
  7. 7.
    Zhao, X., Yi, Y., Erdogan, A.T., Arslan, T.: Dual-core reconfigurable demosaicing engine for next generation of portable camera systems. In: Conference on Design and Architectures for Signal and Image Processing Conference (DASIP), pp. 289–294 (2010)Google Scholar
  8. 8.
    Rani, K.S., Hans, W.J.: FPGA implementation of bilinear interpolation algorithm for CFA demosaicing. In: International Conference on Communications and Signal Processing (ICCSP), pp. 857–863 (2013)Google Scholar
  9. 9.
    Karloff, A., Muscedere, R.: A low-cost, real-time, hardware-based image demosaicking algorithm. In: IEEE International Conference on Electro/Information Technology (EIT), pp. 146–150 (2009)Google Scholar
  10. 10.
    DS643: LogiCORE IP Multi-Port Memory Controller (MPMC) (v6.03.a), Xilinx Inc. (March 2011)Google Scholar
  11. 11.
    Fahmy, S.A.: Generalised Parallel Bilinear Interpolation Architecture for Vision Systems. In: International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 331–336 (2008)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Jalal Khalifat
  • Ali Ebrahim
  • Tughrul Arslan

There are no affiliations available

Personalised recommendations