Verification of Solid State Interlocking Programs

  • Phillip James
  • Andy Lawrence
  • Faron Moller
  • Markus Roggenbach
  • Monika Seisenberger
  • Anton Setzer
  • Karim Kanso
  • Simon Chadwick
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 8368)


We report on the inclusion of a formal method into an industrial design process. Concretely, we suggest carrying out a verification step in railway interlocking design between programming the interlocking and testing this program. Safety still relies on testing, but the burden of guaranteeing completeness and correctness of the validation is in this way greatly reduced. We present a complete methodology for carrying out this verification step in the case of ladder logic programs and give results for real world railway interlockings. As this verification step reduces costs for testing, Invensys Rail is working to include such a verification step into their design process of solid state interlockings.


Model Check Safety Condition Label Transition System Verification Condition Temporal Induction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



Our thanks go to Ulrich Berger for advice on the semantics of ladder logic formulae.


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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Phillip James
    • 1
  • Andy Lawrence
    • 1
  • Faron Moller
    • 1
  • Markus Roggenbach
    • 1
  • Monika Seisenberger
    • 1
  • Anton Setzer
    • 1
  • Karim Kanso
    • 2
  • Simon Chadwick
    • 3
  1. 1.Swansea Railway Verification GroupSwansea UniversityWalesUK
  2. 2.Critical Software TechnologiesSouthamptonEngland, UK
  3. 3.Invensys RailChippenhamEngland, UK

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