Efficient Hardware Implementation of 1024 Point Radix-4 FFT
Since FFT algorithm is extremely demanding task and has several applications in the areas of signal processing and communication systems, it must be precisely designed to induce an efficient implementation of the parameters involving area and performance. To fulfill this requirement an optimized architecture is demonstrated in this paper for computing 1024-point, Radix-4 FFT using FPGA and is majorly compared with Xilinx LogiCoreTM FFT IP and found that proposed design is more efficient and effective in terms of area and performance. A novel architecture referred to as 2-D Vector Rotation and Complex Math Processor has been proposed in this paper. This single structure rotation helps in effectively carrying out the complex multiplications. The algorithm implements multiplexor hardware for computing the complex multipliers, thus consuming the minimal hardware resources. The entire RTL design is described using Verilog HDL and simulated using Xilinx ISim[TM]. This experimental result is tested on Spartan-6 XC6SLX150T. The result shows 557 LUT’s, 837 Flip Flops, 3 DSP Slices, Maximum Frequency of 215 MHz. This is about 52% improvement in resource usage and 5% upgrade in the performance.
KeywordsFPGA FFT 2-D Vector Rotation Complex Math Processor
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