A Novel Design of Low-Power Double Edge-Triggered Flip-Flop
Flip-flops are known and widely used in VLSI integrated circuit (IC) design. The main advantage of using double edge-triggered flip-flop (DETFF) is that it allows one to maintain a constant throughput while operating at only half the clock frequency. As the increasing usages for flip-flops, the desire to reduce power consumption has led to increased demand for low power consumption flip-flops. This paper compares four previously published DETFFs together with our design for their power consumption. Several HSPICE simulations with different input sequences show that the proposed DETFF reduces power consumption up to 79.5 %, as compared to the existing DETFFs.
KeywordsDouble edge-triggered flip-flop (DETFF) Power consumption Power-delay product (PDP) Single edge-triggered flip-flop (SETFF)
The authors deeply acknowledge final support in part from National Science Council, Taiwan, ROC, under contract NSC 102-2622-E-164-002-CC3.
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