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IC and System ESD Co-design

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System Level ESD Protection
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Abstract

The trend towards high level integration of the system functional blocks on-chip is eliminating the barrier between the components and systems. System-on-chip (SoC) and system-in-package (SiP) designs now often combine a variety of analog and digital circuit blocks that can directly interface with system ports and therefore may require system level ESD protection capability.

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Correspondence to Vladislav Vashchenko .

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© 2014 Springer International Publishing Switzerland

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Vashchenko, V., Scholz, M. (2014). IC and System ESD Co-design. In: System Level ESD Protection. Springer, Cham. https://doi.org/10.1007/978-3-319-03221-4_5

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  • DOI: https://doi.org/10.1007/978-3-319-03221-4_5

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-03220-7

  • Online ISBN: 978-3-319-03221-4

  • eBook Packages: EngineeringEngineering (R0)

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