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On-Chip System Level ESD Devices and Clamps

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System Level ESD Protection
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Abstract

Design of mixed-signal analog integrated circuits (ICs) often involves a co-design of the internal functional analog circuit blocks, on-chip ESD solutions and even the process integration in case of power optimized technology. Protection of the pins with system-level specification requires an in-depth understanding of a number of rather cross-disciplinary subjects.

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Correspondence to Vladislav Vashchenko .

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© 2014 Springer International Publishing Switzerland

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Vashchenko, V., Scholz, M. (2014). On-Chip System Level ESD Devices and Clamps. In: System Level ESD Protection. Springer, Cham. https://doi.org/10.1007/978-3-319-03221-4_3

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  • DOI: https://doi.org/10.1007/978-3-319-03221-4_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-03220-7

  • Online ISBN: 978-3-319-03221-4

  • eBook Packages: EngineeringEngineering (R0)

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