Abstract
In the previous chapter the major trend toward SoC and SoP integration with system level pins was emphasized. This trend results in the design paradigm shift toward integration of the system level ESD protection capability on-chip. By providing the second stage ESD current capability the on-chip ESD protection can be both used for the IC-system co-design with the PCB components (Chap. 5) or provide a complete system level compliant pin protection.
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© 2014 Springer International Publishing Switzerland
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Vashchenko, V., Scholz, M. (2014). System Level Test Methods. In: System Level ESD Protection. Springer, Cham. https://doi.org/10.1007/978-3-319-03221-4_2
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DOI: https://doi.org/10.1007/978-3-319-03221-4_2
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-03221-4
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