Test Generation for Short-Circuit Faults in Digital Circuits

  • József Sziray
Part of the Studies in Computational Intelligence book series (SCI, volume 530)


In the first part, the paper presents a test calculation principle which serves for producing tests of logic faults in digital circuits. The name of the principle is composite justification. The considered fault model includes stuck-at-0/1 logic faults. Both single and multiple faults are included. In this paper only combinational logic is taken into consideration. The computations are performed at the gate level. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program. The first part serves for presenting the basic principle which is used in the second part of the paper. The second part deals with another fault class, namely, short-circuit or bridging faults. A short circuit is an erroneous galvanic connection between two circuit lines. Here, a new algorithm is presented for generating tests, where the composite justification is extended to handle this type of faults, as well.


Test-pattern generation Logic faults Short-circuit faults  Multi-valued logic Digital circuits 


  1. 1.
    Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. Computer Science Press, Piscataway (1990)Google Scholar
  2. 2.
    Sziray, J.: Test calculation for logic and delay faults in digital circuits. In: Proceedings of the IEEE Microprocessor Test and Verification Workshop, (MTV-06), pp. 20–29, Austin (2006)Google Scholar
  3. 3.
    Sziray, J.: Test Design of Digital Systems. Széchenyi University Press, Győr (2012)Google Scholar
  4. 4.
    Roth, J.P.: Diagnosis of automata failures: a calculation and a method. IBM J. Res. Dev. 10, 278–291 (1966)CrossRefMATHGoogle Scholar
  5. 5.
    Breuer, M.A., Friedman, A.D.: Functional level primitives in test generation. IEEE Trans. Comput. C-29, 223–235 (1980)Google Scholar
  6. 6.
    Lewis, H.R., Papadimitriou, C.H.: Elements of the Theory of Computation. Prentice-Hall, Upper Saddle River (1998)Google Scholar
  7. 7.
    Drechsler, R., Eggersglüss, S., Fey, G., Tille, D.: Test Pattern Generation Using Boolean Proof Engines. Springer, Heidelberg (2009)Google Scholar
  8. 8.
    Sziray, J., Nagy, Zs.: OPART: a hardware-description language for test generation. In: Nunez, P. (ed.) Microprocessing and Microprogramming, pp. 525–530. North-Holland, Amsterdam (1991)Google Scholar
  9. 9.
    Sallay, B., Petri, A., Tilly, K., Pataricza, A., Benyó, B., Sziray, J.: High level test pattern generation for VHDL circuits. In: Proceedings of the IEEE European Test Workshop’96, pp. 201–205, Montpellier, June 1996Google Scholar
  10. 10.
    Benyó, B., Sziray, J.: The use of VHDL models for design verification. In: Proceedings of the IEEE European Test Workshop, pp. 289–290, Cascais, 23–26 May 2000Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Department of InformaticsSzéchenyi UniversityGyőrHungary

Personalised recommendations