Skip to main content

Application Mapping in Network-on-Chip Using Evolutionary Multi-objective Optimization

  • Chapter
Hardware for Soft Computing and Soft Computing for Hardware

Part of the book series: Studies in Computational Intelligence ((SCI,volume 529))

Abstract

Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In the platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this chapter, we use multi-objective evolutionary optimization to address the problem of mapping topologically pre-selected sets IPs, which constitute the set of optimal solutions that were found for the IP assignment problem, on the tiles of a mesh-based NoC. The IP mapping optimization is driven by the area occupied, execution time and power consumption.

This chapter was developed in collaboration with Marcus Vinícius Carvalho da Silva.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Deb, K., Pratap, A., Agarwal, S., Meyarivan, T.: A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE-EC 6, 182–197 (2002)

    Google Scholar 

  2. Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: Task Graphs For Free. In: Proceedings of the 6th International Workshop on Hardware/Software Co-design, pp. 97–101. IEEE Computer Society, Seattle (1998)

    Google Scholar 

  3. Dijkstra, E.W.: A note on two problems in connexion with graphs. Numerische Mathematik 1, 269–271 (1959)

    Article  MathSciNet  MATH  Google Scholar 

  4. Hu, J., Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: ASPDAC: Proceedings of the 2003 Conference on Asia South Pacific Design Automation, pp. 233–239. ACM, New York (2003)

    Chapter  Google Scholar 

  5. Jena, R.K., Sharma, G.K.: A multi-objective evolutionary algorithm based optimization model for network-on-chip synthesis. In: ITNG, pp. 977–982. IEEE Computer Society (2007)

    Google Scholar 

  6. Kumar, S., Jantsch, A., Millberg, M., Öberg, J., Soininen, J.-P., Forsell, M., Tiensyrjä, K., Hemani, A.: A network on chip architecture and design methodology. In: ISVLSI, pp. 117–124. IEEE Computer Society (2002)

    Google Scholar 

  7. Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: DSD, pp. 180–189. IEEE Computer Society (2003)

    Google Scholar 

  8. Murali, S., Micheli, G.D.: Bandwidth-constrained mapping of cores onto NoC architectures. In: DATE, pp. 896–903. IEEE Computer Society (2004)

    Google Scholar 

  9. Pareto, V.: Cours D’Economie Politique. F. Rouge, Lausanne (1896)

    Google Scholar 

  10. Zhou, W., Zhang, Y., Mao, Z.: Pareto based multi-objective mapping IP cores onto NoC architectures. In: APCCAS, pp. 331–334. IEEE (2006)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Nadia Nedjah .

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Nedjah, N., de Macedo Mourelle, L. (2014). Application Mapping in Network-on-Chip Using Evolutionary Multi-objective Optimization. In: Hardware for Soft Computing and Soft Computing for Hardware. Studies in Computational Intelligence, vol 529. Springer, Cham. https://doi.org/10.1007/978-3-319-03110-1_10

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-03110-1_10

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-03109-5

  • Online ISBN: 978-3-319-03110-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics