Reconfigurable Multichannel Down Convertor for on Chip Network in MRI

Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 248)

Abstract

Reconfigurable multi channel down convertor for on- chip network in MRI has been designed and developed in this paper. The convertor is extendable up to 128 channels using direct Re-use FIR filter, requiring less routing area, less static and dynamic power and finally, less delay. The system developed is superior to existing model in terms of high power consumption, large delay& limited channels up to 8 channels. We have reduced the power consumption in this model using placement & routing algorithm. It is done by creating the separate P blocks in the existing model. The existing 8 channel model consumes 3092.1mw (static power 3092.1mw & dynamic 42.6 mw). After applying three different routing & placement algorithms on 8 channels model namely global routing, channel routing and river routing the power consumed results 2608.2mw (static power 2608.2mw & dynamic 34.6mw), 04.5mw (static power 68.8mw & dynamic 35.7mw) and 100.5mw (static power 64.9mw & dynamic 35.6mw) respectively. In an extended work the authors have tried and successfully executed the model and system for 128 channels for MRI applications. The proposed model is first designed on simulink platform using Xilinx blackest and then it is transferred on FPGA platform using system generator. The complete circuit is synthesized, implemented, simulated using Xilinx design suite.

Keywords

DDC DUC FIR filter LTI system. Routing Algorithm P block 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Department of Electronics and Communication, College of Technology and EngineeringMaharana Pratap University Agriculture and TechnologyUdaipurIndia

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