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Improved Underlap FinFET with Asymmetric Spacer Permittivities

  • Saurabh K. Nema
  • M. SaiKiran
  • P. Singh
  • Archana Pandey
  • S. K. Manhas
  • A. K. Saxena
  • Anand Bulusu
Part of the Environmental Science and Engineering book series (ESE)

Abstract

A much higher performance can be achieved by the use of a high-K spacer for only the SE region of the Underlap FinFET. We explain this effect using a 3-transistor equivalent circuit in the FinFET device. Our new device design does not increase OFF state current.

Keywords

Underlap FinFET High-K spacer Delay Ion Ioff 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Saurabh K. Nema
    • 1
  • M. SaiKiran
    • 2
  • P. Singh
    • 2
  • Archana Pandey
    • 2
  • S. K. Manhas
    • 2
  • A. K. Saxena
    • 2
  • Anand Bulusu
    • 2
  1. 1.Cisco SystemsBangaloreIndia
  2. 2.Department of Electronics and Communication EngineeringIITRoorkeeIndia

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