On the Voltage Transfer Characteristics (VTC) of some Nanoscale Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs)

  • Jhuma Saha
  • Amrita Kumari
  • Shankaranand Jha
  • Subindu Kumar
Part of the Environmental Science and Engineering book series (ESE)


The voltage transfer characteristics (VTC) of a complementary metal-oxide-semiconductor (CMOS) inverter provides necessary information about some of the most important performance parameters, such as noise margin (low/high), inverter logic threshold voltage, and so on. Over years, there has been an increasing trend to use various commercially available Technology Computer Aided Design (TCAD) tools and circuit simulators to study such performance parameters. The emergence of novel devices has forced the theoretical research community to refine TCAD tools and simulators. We have developed a simulator that can plot the VTC curve of strained/unstrained nanoscale MOSFET based CMOS circuits. Our algorithm can faithfully reproduce the VTC curve of nanoscale MOSFET based CMOS inverter with an average deviation of less than 2 %. We have also shown the dependence of VTC curves of nanoscale strained Si/SiGe and multi channel (MC) gate-all-around (GAA) MOSFET based CMOS inverters on some important device parameters.


MOSFET Inverter Strain Multi-channel and gate-all-around 


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  1. 1.
    TCAD Sentaurus Device User’s Manual, Synopsys, Mountain View, CA, 2005.Google Scholar
  2. 2.
    MEDICI 4.0, Technol. Model. Assoc., Inc., Palo Alto, CA, 1997.Google Scholar
  3. 3.
    PSPICE A/D User’s Guide. Irvine, CA : Microsim Corp., June 1997. Version 8.0.Google Scholar
  4. 4.
    H. Batwani, M. Gaur, and M. J. Kumar, “Analytical drain current model for nanoscale strained-Si/SiGe MOSFETs,” COMPEL, Int. J. Computat. Math. Elect. Electron. Eng., vol. 28, no. 2, pp. 353-371, 2009.CrossRefGoogle Scholar
  5. 5.
    M. J. Kumar, V. Venkataraman, and S. Nawal, “Analytical drain current model of nanoscale strained-Si/SiGe MOSFETs for analog circuit simulation,” In Proc. 20th Int. Conf. on VLSI Design, pp. 189-194, 2007.Google Scholar
  6. 6.
    K. Rim, J. L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si N-MOSFET’s,” IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1406-1415, Jul. 2000.CrossRefGoogle Scholar
  7. 7.
    M. J. Kumar, V. Venkataraman, and S. Nawal, “Impact of strain or Ge content on the threshold voltage of nanoscale strained-Si/SiGe bulk MOSFETs,” IEEE Trans. Device Mater. Rel., vol. 7, no. 1, pp. 181-187, Mar. 2007.CrossRefGoogle Scholar
  8. 8.
    H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, and A. Yakovlev, “Impact of strain on the design of low-power high-speed circuits,” IEEE Int. Symp. Circuits Syst., pp. 1153-1156, May 2007.Google Scholar
  9. 9.
    H. Ramakrishnan, “Strained Silicon Technology for Low-Power High-Speed Circuit Applications,” Sch. Elect. Electron. Comput. Eng., Merz Court, Newcastle Univ., Newcastle Tyne, UK, Tech. Rep. Series NCL-EECE-MSD-TR-2008-140, July 2008.Google Scholar
  10. 10.
    S. Kumar, and S. Jha, “Impact of elliptical cross-section on the propagation delay of multi-channel gate-all-around MOSFET based inverters,” Microelectronics J., vol. 44, pp. 844-851, 2013.CrossRefGoogle Scholar
  11. 11.
    K. D. Buddharaju, N. Singh, S. C. Rustagi, Selin H. G. Teo, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top down approach,” Solid State Electron., vol. 52, pp. 1312-1317, May 2008.CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Jhuma Saha
    • 1
  • Amrita Kumari
    • 1
  • Shankaranand Jha
    • 1
  • Subindu Kumar
    • 1
  1. 1.Department of Electronics EngineeringIndian School of MinesDhanbadIndia

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