Effect of Parasitic Capacitance on DG-HGTFET and Its Influence on Device RF Performance

Conference paper
Part of the Environmental Science and Engineering book series (ESE)

Abstract

In this paper, for the first time, the design of double-gate hetero-gate-dielectric tunnel field effect transistor (DG-HGTFET) for asymmetric drain doping for RF (Radio frequency) application is discussed. The impact of drain parasitic capacitance on the device performance is analyzed. The results indicate that parasitic capacitances are dominating factor which will degrade the RF characteristics. For this, the RF figures of merit for DG-HGTFET are analyzed in terms of unit-gain cut-off frequency (f T ), maximum frequency of oscillation (f max ). Further, asymmetric drain doping is also analyzed for suppressing the ambipolar behavior.

Keywords

Cut-off frequency (fTRadio frequency (RF) Hetero-gate-dielectric tunnel field effect transistor (HG-TFET) 

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References

  1. 1.
    K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, “Vertical tunnel field-effect transistor,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279, Feb. 2004.CrossRefGoogle Scholar
  2. 2.
    A.M.Ionescu,“New functionality and ultra low power: Key opportunities for post-CMOS era,” in Proc. Int. Symp. VLSI Technol., Syst., Appl., 2008, pp. 72–73.Google Scholar
  3. 3.
    S. Agarwal, G. Klimeck, and M. Luisier, “Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 621–623, Jun. 2010.CrossRefGoogle Scholar
  4. 4.
    R. Asra, M. Srivastava, K. V. R. M. Murali, R. K. Pandey, H. Gossner, and V. R. Rao, “A tunnel FET for VDD scaling below 0.6 V with a CMOS comparable performance,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1855–1863, Jul. 2011.CrossRefGoogle Scholar
  5. 5.
    A.M.Ionescu and H.Riel, “Tunnel field-effect transistors as energyefficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, Nov. 2011.CrossRefGoogle Scholar
  6. 6.
    W. Y. Choi and W. Lee, “Hetero-Gate-Dielectric Tunneling Field-EffectTransistors”, IEEE Trans. Electron Devices, Vol. 57, no. 9, pp. 2317-2319, Sept. 2010.CrossRefGoogle Scholar
  7. 7.
    Atlas User’s Manual, Silvaco Int., Santa Clara, CA, April 20, 2010.Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  • Vikas Vijayvargiya
    • 1
  • Santosh Kumar Vishvakarma
    • 1
  1. 1.Nanoscale Devices, VLSI/ULSI Circuit and System Design Lab, Electrical Engineering DisciplineIndian Institute of Technology IndoreIndoreIndia

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