Abstract
Throughout this book, methods and architectures have been discussed for performing pre-bond and post-bond test in 3D SICs. Many of these methods, such as those discussed in Chaps. 4 and 5, were designed to be compatible with emerging test standards. This chapter will explore the emerging standards with regard to stacked dies and test interfaces and their associated test implications. Section 7.2 examines a die test wrapper, based on the IEEE 1500 and IEEE 1149.1 [20, 102] test standards, that is currently being developed by the IEEE P1838 workgroup [103]. Section 7.3 provides an overview of the JEDEC JESD-229 [104] standard developed for memory-on-logic stacks and how the test wrapper described in Sect. 7.2 can be extended for testing a stack that utilizes the JEDEC framework.
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Noia, B., Chakrabarty, K. (2014). Post-Bond Test Wrappers and Emerging Test Standards. In: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-02378-6_7
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DOI: https://doi.org/10.1007/978-3-319-02378-6_7
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