Abstract
Pre-bond testing of individual dies prior to stacking is crucial for yield assurance in 3D-SICs [42, 43]. A complete known-good-die (KGD) test requires testing of die logic, power and clock networks, and the TSVs that will interconnect dies after bonding in the stack.
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References
P.-Y. Chen, W. C.-W. Wu, and D.-M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC Before Bonding”, Proc. IEEE VLSI Test Symposium, pp. 263–268, 2010.
D. Lewis and H.-H. Lee, “A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors”, Proc. International Test Conference, pp. 1–8, 2007.
H. Chen, J.-Y. Shih, S.-W. Li, H.-C. Lin, M.-J. Wang, C.-N. Peng. “Electrical Tests for Three-Dimensional ICs (3DICs) with TSVs.”, International Test Conference 3D-Test Workshop, 2010.
M. Cho, C. Liu, D. Kim, S. Lim, and S. Mukhopadhyay, “Design Method and Test Structure to Characterize and Repair TSV Defect-Induced Signal Degradation in 3D System”, Proc. IEEE Conference on Computer-Aided Design, pp. 694–697, 2010.
E.J. Marinissen and Y. Zorian, “Testing 3D Chips Containing Through-Silicon Vias”, International Test Conference, E 1.1, 2009.
H.-H.S. Lee and K. Chakrabarty, “Test Challenges for 3D Integrated Circuits”, IEEE Design & Test of Computers, vol. 26, pp. 26–35, September/October 2009.
K. Lee, “Trends in Test”, Keynote talk presented at IEEE Asian Test Symposium, December 2010.
45nm PTM LP Model. http://ptm.asu.edu/modelcard/LP/45nm_LP.pm Accessed January 2011.
L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, and W.-T. Cheng, “Oscillation-Based Prebond TSV Test”, IEEE Transactions on Computer-Aided Design, vol.32, no.9, pp. 1440–1444, 2013.
S. Deutsch and K. Chakrabarty, “Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels”, Proc. Design, Automation, and Test Conference in Europe, pp. 18–22, 2013.
T. Thorolfsson et al., “Design Automation for a 3DIC FFT Processor for Synthetic Aperture Radar: A Case Study”, Proc. IEEE Design Automation Conference, 2009.
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Noia, B., Chakrabarty, K. (2014). Built-In Self-Test for TSVs. In: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-02378-6_3
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DOI: https://doi.org/10.1007/978-3-319-02378-6_3
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