Analysis and Comparison in the Energy-Delay-Area Domain

Abstract

In this chapter, results relative to an extensive comparison in a 65 nm CMOS technology of existing FFs classes and topologies are reported. In contrast to previous investigations, the analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff such as leakage and layout and interconnect impact. The analysis involves a significantly wider range of FF classes and topologies. The tradeoffs between leakage, area, clock load, delay and other interesting properties are extensively discussed. The investigation permits to derive several considerations on each FF class and to identify the best topologies for a targeted application.