Feasibility Study of Future HPC Systems for Memory-Intensive Applications
After the successful launch of K-Computer in Japan, the Japanese government started a new R&D program entitled “Feasibility Study of Future HPCI Systems.” In this program, social and scientific demands for HPC in the next 5–10 years will be addressed, and HPC systems that satisfy the demands and key technologies to develop such systems will be discussed and evaluated. Currently, three system design teams get involved in this program, and this article present a HPC project entitled “Feasibility Study of Future HPC Systems for Memory Intensive Applications,” which is conducted by a team of Tohoku University, JAMSTEC and NEC.
KeywordsMemory Bandwidth Peak Performance Memory Subsystem Vector Processor Roof Line
Many colleagues get involved in this project, and great thanks go to Dr. Y. Kaneda and Dr. K. Watanabe of JAMSTEC (Japan Agency for Marine-Earth Science and Technology) as co-leaders of the application group, Professor M. Koyanagi of Tohoku University as the leader of the 2.5D/3D device group, and Ms. Y. Hashimoto of NEC as the leader of the NEC application, system and device design group. This project is supported by MEXT.
- 1.M. Floyd et al. Harnessing the Adaptive Energy Management Features of the POWER7 chip. In HOT Chips 2010, 2010.Google Scholar
- 3.Oded Lempel. 2nd Generation Intel* Core* Processor Family: Intel Core i7, i5 and i3. In HOT Chips 2011, 2011.Google Scholar
- 4.Takumi Maruyama. SPARC64(TM) Viiifx: Fujitsu’s New Generation Octo Core Processor for PETA Scale Computing. In HOT Chips 2009, 2009.Google Scholar
- 5.MEXT HPC Task Force. (in Japanese) Report on Application R&D Roadmap for Exascale Computing. 2012.Google Scholar
- 6.S. Momose. Next Generation Vector Supercomputer for Providing Higher Sustained Performance. In COOL Chips 2013, 2013.Google Scholar
- 7.Top 500 Supercomputer Sites. http://www.spec.org/.