Abstract
Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-2001 [IEEE01, Maun90], is a collection of design rules applied principally at the Integrated Circuit (IC) level that allow software to alleviate the growing cost of designing, producing and testing digital systems. A fundamental benefit of the standard is its ability to transform extremely difficult printed circuit board testing problems that could only be attacked with Ad-Hoc testing methods [Will83] into well-structured problems that software can easily and swiftly deal with.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
Informally, the Standard is often referred to as the “JTAG ” proposal, due to its history of development. JTAG was the Joint Test Action Group made up of companies primarily in Europe and North America. This group created the foundation for the IEEE work.
- 2.
In this portion of this book, the term “Standard” shall refer to 1149.1. Later we will switch our attention to 1149.4, 1149.6 and 1532.
- 3.
There were many examples of proprietary test systems in existence well before this time, typically at the larger, vertically integrated electronics manufacturers.
- 4.
The quality of this “assurance” varies wildly from place to place. In some instances, the effectiveness is good. In other cases, this last test step may be nearly useless, serving mainly as a psychological comfort, or the fulfillment of some contractual agreement.
- 5.
In the early days of simulation (late 1960s) simple gate level models or systems of Boolean logic equations were used to describe circuits. Now there is a range of technology spanning transistor level models to high level behavioral models.
- 6.
“Faults” are an abstraction. The most popular fault model is the Single Stuck-at fault model. Considering multiple Stuck-at faults is explosively combinatorial and quickly become intractable. Thus, “all faults” means “all faults that are practical to consider.”
- 7.
Automatic Test Generation software has had marginal success in supplanting humans in this task. In cases where strict design rules are obeyed, automation can be achieved. For many electronics manufacturers, this has not been practical.
- 8.
Stimulating embedded nodes requires the ability to overdrive the states that upstream ICs may be driving. This “backdrive” capability requires tester drivers that can source/sink in excess of 700 milliamperes of current (at speed) for many of today’s logic families.
- 9.
When targeting IC pins, the test probes often do not look like sharpened nails , but instead have a variety of machined surfaces that are circular and contain a “waffle” pattern of small, sharpened points that will not slip off the targeted pin/solder surface. This surface, in time will collect solder flux and other debris leading to contact problems. Today’s nails are usually targeted at specific test pads and have a single (very) sharp point.
- 10.
A “via” is a cylindrical conductor that makes a physical connection between segments of a node on different layers of a printed circuit board. Most vias traverse the entire thickness of the board and are thus visible to In-Circuit nails . These are referred to as “natural” test points [Bull87]. Those that do not pierce the entire thickness and are not visible from the outside are called “blind” vias.
- 11.
In the literature, the term “System Logic ” has a number of synonyms. Some are “core logic”, “internal logic”, and “mission logic”. Currently, with the attention attracted by the 1149.4 Analog Test Bus Standard, there is a move to replace “logic” with “circuitry”.
- 12.
With the advent of the 2013 version of 1149.1 Boundary-Scan, the concept of “Test Mode Persistence” has been introduced to give test engineers a tool to manage post-testing activities on boards. See Sect. 11.3.4.1 in Part 2 of this book.
- 13.
As in the Standard itself, signals that are asserted or active in the low state will have an asterisk suffix. All others are asserted in the high state.
- 14.
Making TRST* optional allows the tradeoff of having an asynchronous reset for the TAP versus the cost of adding a fifth pin.
- 15.
This requirement implies the use of internal pull-ups on these pins, which drain current. There are two negatives to this that sometimes tempt designers to ignore the float-high rule; first, in ultra-low power systems (for example, battery-powered), the extra power drain is a concern. Second, the quiescent current consumption in CMOS ICs (IDDQ ) is significantly higher which frustrates IDDQ testing [Hawk85], an example of two testing methodologies in conflict. These negatives can be mitigated with clever design. For example, as an extension of the standard, a designer could provide a mode that turns off the pull-ups for IDDQ testing.
- 16.
An exception to this occurs if the device has “Test Mode Persistence” enabled. See Sect. 11.3.4.1 in Part 2 of this book.
- 17.
Upon entering Test-Logic-Reset by means of clocking TCK, it is necessary to return TCK to 0 (a falling edge) to completely reset certain portions of the 1149.1 logic that are sensitive to falling edges of TCK. TRST* on the other hand completely resets all 1149.1 circuitry immediately.
- 18.
- 19.
Registers are constructed with dual ranks, a shiftable part and a hold part to prevent rippling , due to shifting, from being visible to downstream logic. When we say a register is selected or shifted, we mean the shift portion of it which is connected between TDI and TDO.
- 20.
Throughout this book, any pattern of bits will be displayed with the most significant bit on the left, through to the least significant on the right. The least significant bit would be the first bit shifted into TDI or out from TDO.
- 21.
Another approach to solving this problem is to simply stop the TCK signal (in the low state) while in Shift-IR while overhead activities are processed. However, some Boundary-Scan masters may not be capable of halting TCK.
- 22.
As before with instruction shifting, we could simply stop the TCK signal (in the low state) while in Shift-DR while overhead activities are processed if stopping TCK is supported.
- 23.
The meaning of “write” operation will become clearer in the description of the Boundary Register .
- 24.
The parallel output stage can be implemented with a simpler latch. The shift register element must be a full edge-triggered design or equivalent.
- 25.
However, if an instruction is marked private then the size and purpose of a target register may or may not be documented. (See Sect. 2.3.12.)
- 26.
The initial release of IEEE 1149.1 [IEEE90] did not have this restriction. Then, it was allowable to have some drivers enabled and others disabled simultaneously by a single control cell. This caused problems for test algorithms and decreased fault coverage so in 1993, this restriction was added [IEEE93].
- 27.
The flawed cell is named “BC_6” in BSDL . Designers should avoid using it. The improved cell is called “BC_7”. (See Sect. 2.6.3 on page 97.) Indeed, with the 2013 update of 1149.1, this cell is officially unsupported, and erased from the supporting BSDL package STD_1149_1_2013.
- 28.
Care must be taken to assure that on transitioning from PRELOAD to EXTEST (at Update-IR), that the update latch does indeed load the content of the Capture Flip-Flop.
- 29.
Without proper design care, this driver structure could interact with external circuitry (passive or active) to form an oscillator. If the output portion of this driver was implemented in stages of successively larger buffers, an internal stage could have the latching property and the final stage would isolate the latch (feedback) from outside influences. This would remove the “anti-stress” feature of the Whetsel driver however.
- 30.
See also the notion of a “Digital Boundary Module” introduced in Sect. 7.2.5 on page 246 by the 1149.4 standard.
- 31.
Exceptions could occur when some of the ICs have an optional TRST* pin. We assume all ICs are synchronized to Test-Logic-Reset and that no assertions are made to TRST*.
- 32.
If a Pin-Permission mode has been entered, it may be necessary to perform a reset upon both the Boundary-Scan logic and the System Logic before the System Logic will operate normally. In some cases, the surest, safest way of achieving this is by cycling the power.
- 33.
The Standard also states that all unused instruction codes not declared to be private must also decode to BYPASS .
- 34.
There is a code (00001111111) reserved by 1149.1 and considered an “illegal” manufacturer’s code. This code can be fed into the TDI of a chain of devices of unknown composition so that when it finally appears at TDO, you then know you have scanned out all the devices in the chain.
- 35.
The actual list of manufacturer’s ID numbers maintained by JEDEC has more bits, so this 11-bit field is a compression and allows for only 2048 unique numbers. It could happen that two unique devices could appear some day with identical IDCODE values, but the probability is low that this will ever cause confusion in testing boards and systems.
- 36.
This is much easier to accomplish if a second–source agreement is based upon the exchange of design data (that can be re-synthesized) rather than based upon exchanging mask data.
- 37.
SAMPLE and PRELOAD , in previous releases of the Standard since the beginning [IEEE90], were one instruction with one opcode. (It was called “SAMPLE/PRELOAD”.) In a long ranging debate, the 1149.1 Working Group has now divorced the two instructions so that each can be independently encoded and implemented. This lays the groundwork for a possible future demotion of SAMPLE from mandatory to optional status. (PRELOAD will remain mandatory.) There are subtle implications of this move which are controversial within the Working Group and still subject to much debate. It is possible and permissible however to merge the design of SAMPLE with PRELOAD so that the same opcode does both functions. This is likely to be how these instructions will be treated until SAMPLE is (if ever) demoted.
- 38.
The 2013 update of 1149.1 provides an additional resource for this problem called “Test Mode Persistence”. See Sect. 11.3.4.1 in Part 2 of this book.
- 39.
Also, an input cell on a bidirectional I/O pin will capture that pin’s state.
- 40.
Note the Standard only requires EXTEST to capture IC inputs (and bidirectionals) but does not specify what must be captured by control or output cells. This will allow us to merge the behavior of EXTEST with INTEST so that the two instructions can be implemented with a single opcode. Another option is to implement self-monitoring outputs (see Sect. 5.1.5 on page 180) if INTEST is not implemented.
- 41.
This option must be chosen if a merger of EXTEST and INTEST behavior is desired.
- 42.
These tests are not the same as those applied by an IC tester in parallel to the component I/O pins. The tests must be prepared for the System Logic I/O signals. For each bus or bidirectional pin, there may be several System Logic I/O signals.
- 43.
Actually, if the outputs are disabled which is an option offered by the Standard, this might not be perfectly true. Disabled outputs may seem safe but downstream board logic may be confused by high impedance values on their inputs.
- 44.
This IC is one of several in a family (called the SCOPE octals) that all implement the same extensions. SCOPE is a trademark of Texas Instruments.
- 45.
Another concern is the routing of global signals such as ClockDR, ShiftDR, UpdateDR and Mode (see Fig. 1.7 on page 22). These signals must be routed to every Boundary Register cell. Note that once a routing channel has been found for one signal, adding more is considerably easier.
- 46.
The price for eliminating these multiplexers may be the inability to implement the optional INTEST instruction. However, the value of INTEST to anyone beyond the original manufacturer is debatable and many original manufacturers use internal scan techniques rather than INTEST anyway.
- 47.
This device is also an example of one that has special initialization requirements. See Sect. 10.11 for a discussion of this topic, which is becoming more important with System-on-Chip technology. This device is faster (by a decade) than the upper bound on practical Boundary-Scan implementations that some have claimed to the author.
- 48.
Indeed, if more people are wary, improvements will come faster!
- 49.
I am told that Vishwani Agrawal originated this phrase. It beautifully sums up the fact that placing some responsibility for the economic success of a product on the design team can solve many of our testing problems. This usually requires enlightened management support.
References
“Test Generation for VLSI Chips”, V. D. Agrawal and S. C. Seth, IEEE Computer Society Press, Los Alamitos CA, 1988
“Am29030 and Am29035 Microprocessors User's Manual and Data Sheet”, Advanced Micro Devices, Inc. 1991
“Implementing 1149.1 on CMOS Microprocessors”, W. C. Bruce, M. G. Gallup, G. Giles and T. Munns, Proceedings, International Test Conference, Nashville TN, pp 879–886, Oct 1991
“Designing SMT Boards for In-Circuit Testability”, M. Bullock, Proceedings, International Test Conference, pp 606–613, Washington DC, Sept 1987
“Using Boundary-Scan Description Language in Design”, D. Chiles and J. DeJaco, Proceedings, International Test Conference, pp 865–868, Nashville TN. Oct 1991
“A Structured Graphical Tool for Analyzing Boundary-Scan Violations”, M. Cogswell, S. Mardhani, K. Melocco and H. Arora, Proceedings, International Test Conference, Baltimore MD, 755–762, Oct 2002
“Printed Circuits Handbook, 5th Edition”, C. F. Coombs, Editor, McGraw-Hill, New York, 2001
“ASIC Testing in a Board/System Environment”, F. P. Fasang, IEEE Custom Integrated Circuits Conference, New York NY, pp 22.4.1–22.4.4, 1989
“The Testability Features of the 68040”, M. Gallup et al, Proceedings, International Test Conference, pp 749–757, Washington DC, Sept 1990
“Prototype Testing Simplified by Scannable Buffers and Latches”, A. Halliday, G. Young and A. Crouch, Proceedings, International Test Conference, pp 174–181, Washington DC, Aug 1989
“The Impact of Boundary-Scan on Board Test Strategies”, P. Hansen, Proceedings, ATE&I Conference, Boston MA. pp 35–40, June 1989
“Testing Conventional Logic and Memory Clusters Using Boundary-Scan Devices as Virtual ATE Channels”, P. Hansen, Proceedings, International Test Conference, Washington DC, pp 166–173, Aug 1989
“Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs”, C. F. Hawkins and J. M. Soden, Proceedings, International Test Conference, pp 544–555, Philadelphia, Nov 1985
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1–1990, IEEE Standards Board, 345 East 47th St. New York NY 10017, May 1990
“Extended Digital Serial Subset”, Proposed IEEE Standard P1149.2/D0.2, IEEE Standards Board, 345 East 47th St. New York NY 10017, Feb 1992
“IEEE Standard 1149.1 Draft Supplement”, IEEE Standard 1149.1a-1993, IEEE Standards Board, 345 East 47thSt. New York NY 10017, 1993 (Now included in [IEEE01])
“IEEE Standard VHDL Language Reference”, IEEE Standard 1076-1987, IEEE Standards Board, 345 East 47th St. New York NY 10017, 1993
“IEEE Standard Module Test and Maintenance (MTM) Bus Protocol”, IEEE Standard 1149.5-1995, IEEE Standards Board, 345 East 47th St. New York NY 10017, 1995
“IEEE Standard for a Mixed Signal Test Bus”, IEEE Standard 1149.4-1999, IEEE Standards Board, 345 East 47th St. New York NY 10017, 1999
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1-2001, IEEE Standards Board, 345 East 47th St. New York NY 10017, 2001
“IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks”, IEEE Standard 1149.6-2003, IEEE Standards Board, 345 East 47th St. New York NY 10017, 2003
“Intel486 DX Microprocessor Data Book”, Intel Corporation, June 1991
“Standard Manufacturer's Identification Code”, Joint Electron Device Engineering Council, JEDEC Publication 106-A, Washington DC, 1986
“Practical Test Generation with IEEE 1149.1 Boundary-Scan”, H. Kajitani, H. Sato, H. Saito and S. Oresjo, Proceedings, ATE&I Conference, pp 10–17, Anaheim CA. Jan 1992
“Improved Digital I/O Ports Enhance Testability of Interconnections”, A. Kristof, Proceedings, International Test Conference, Baltimore MD, 763–772, Oct 2002
“A Good Excuse for Reuse: 'Open' TAP Controller Design”, D. Lavo, Proceedings, International Test Conference, Atlantic City NJ, pp 1090–1099, Oct 2000
“Functional Test and Diagnosis: A Proposed JTAG Sample Mode Scan Tester”, M. F. Lefebvre, Proceedings, International Test Conference, pp 294–303, Washington DC, Sept 1990
“The Test Access Port and Boundary-Scan Architecture”, C. M. Maunder and R. E. Tulloss, IEEE Computer Society Press, Los Alamitos CA, Sept 1990
“Success with Boundary-Scan, A Case Study”, P. Milo, Evaluation Engineering, pp 72–74, Feb 1995
“Signature Analysis - Concepts, Examples and Guidelines”, H. J. Nadig, Hewlett-Packard Journal, pp 15–21, May 1977
“Board Test Issues when Implementing Boundary-Scan IEEE 1149.1”, S. Oresjo and J. Stoltman, Proceedings, ATE&I Conference, pp 207–213, Anaheim CA. Jan 1992
“Integrating Design and Test: Using CAE Tools for ATE Programming”, K. P. Parker, IEEE Computer Society Press, Los Alamitos CA, 1987
“The Impact of Boundary-Scan on Board Test”, K. P. Parker, IEEE Design and Test of Computers, vol 6, pp 18–30, August 1989
“Production Board Testing in a Boundary-Scan Environment”, K. P. Parker, Proceedings, ATE&I Conference, Anaheim CA. pp 11–18, Jan 1990
“Design, Fabrication and Use of Mixed-Signal IC Testability Structures”, K. P. Parker, J. E. McDermid, R. A. Browen, K. Nuria, K. Hirayama, A. Matsuzawa, Proceedings, International Test Conference, pp 489–498, Washington DC, Nov 1997
“System Issues with Boundary-Scan Board Test”, K. P. Parker, Proceedings, International Test Conference, pp 724–728, Atlantic City NJ, Oct 2000
“A New Probing Technique for High-Speed/High-Density Printed Circuit Boards”, Parker, K. P., Proceedings, International Test Conference, paper 13.1, Charlotte NC, Oct 2004
“Bead Probes in Practice”, Parker, K. P., Proceedings, International Test Conference, Austin TX, Nov 2005
“Surviving State Disruptions Caused by Test: the “Lobotomy Problem”, Parker, K. P., Proceedings, International Test Conference, paper 19.2, Austin TX, Oct 2010
“Surviving State Disruptions Caused by Test: A Case Study”, Parker, K. P., Kameyama, S., Dubberke, D., Proceedings, International Test Conference, Paper 5.2, Anaheim CA, Sept 2011
“A Design-For-Testability Architecture for Multichip Modules”, K. E. Posse, Proceedings, International Test Conference, pp 113–121, Nashville TN, Oct 1991
“Interconnect Testing of Boards with Partial Boundary-Scan”, G. D Robinson, J. G. Deshayes, Proceedings, International Test Conference, pp 572–581, Washington DC, Sept 1990
“An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-compliance Improvements”, D. Stang and R. Dandapani, Proceedings, International Test Conference, Baltimore MD, 746–753, Oct 2002
“JTAG Boundary-Scan: Diagnosing Module Level Functional Failures”, J. Sweeney, National Communications Conference, 1988, pp 1801–1804
“54BCT8244/74BCT8244 Octal Buffer with Boundary-Scan”, Texas Instruments, Inc., 1991
“54BCT8374/74BCT8374 Octal D Flip-Flop with Boundary-Scan”, Texas Instruments, Inc., 1991
“Improved Boundary Scan Design”, L. Whetsel, Proceedings, International Test Conference, pp 851–860, Washington DC, Oct 1995
“Design for Testability — A Survey”, T. W. Williams and K. P. Parker, Proceedings of the IEEE, vol. 71, No. 1, Jan 1983
“XC 4000 Logic Cell Array Family”, Xilinx Inc. 1990
“Boundary-Scan Emulator for XC 3000”, Application Note XAPP-007.0, Xilinx Inc. 1992
“The Programmable Logic Data Book”, Xilinx Inc, 1998
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Parker, K.P. (2016). Boundary-Scan Basics and Vocabulary. In: The Boundary-Scan Handbook. Springer, Cham. https://doi.org/10.1007/978-3-319-01174-5_1
Download citation
DOI: https://doi.org/10.1007/978-3-319-01174-5_1
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-01173-8
Online ISBN: 978-3-319-01174-5
eBook Packages: EngineeringEngineering (R0)