Power Management in Adaptive Pipelined MPSoCs



System-level power management schemes are often deployed in MPSoCs to exploit the idleness of processors at run-time for energy reduction by putting idle processors in low-power states [1, 2]. These schemes decide “when" and “which" power state should be selected for a processor to maximally reduce the energy consumption of the MPSoC. The decision is a challenging one due to the latency and energy overheads involved in a transition from one power state to another. The aim of this chapter is to propose a power manager for an adaptive pipelined MPSoC to select the most suitable power state for each of the idle auxiliary processors.


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© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.School of Computer Science and EngineeringUniversity of New South WalesKensingtonAustralia

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