Abstract
A pipelined MPSoC’s stages need to be balanced for maximal utilisation of the processors to achieve high throughput with reduced area footprint and reduced power consumption. This chapter addresses the problem of optimising a pipelined MPSoC’s area footprint.
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Javaid, H., Parameswaran, S. (2014). Design Space Exploration of Pipelined MPSoCs. In: Pipelined Multiprocessor System-on-Chip for Multimedia. Springer, Cham. https://doi.org/10.1007/978-3-319-01113-4_5
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DOI: https://doi.org/10.1007/978-3-319-01113-4_5
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