Performance Estimation of Pipelined MPSoCs

Chapter

Abstract

This chapter focuses on analytical models and estimation methods for three performance metrics (execution time, latency and throughput) of pipelined MPSoCs to speed up their design space exploration process.

References

  1. 1.
    S.L. Shee, S. Parameswaran, Design methodology for pipelined heterogeneous multiprocessor system, in DAC ’07: Proceedings of the 44th annual conference on Design automation, San Diego, pp. 811–816 2007Google Scholar
  2. 2.
    I. Karkowski, H. Corporaal, Design of heterogenous multi-processor embedded systems: applying functional pipelining, in PACT ’97: Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques, IEEE Computer Society, San Francisco, 1997Google Scholar
  3. 3.
    H. Javaid, S. Parameswaran, Synthesis of heterogeneous pipelined multiprocessor systems using ilp: jpeg case study, in CODES/ISSS ’08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, ACM, New York, pp. 1–6 2008Google Scholar
  4. 4.
    H. Javaid, S. Parameswaran, A design flow for application specific heterogeneous pipelined multiprocessor systems, in DAC ’09: Proceedings of the 46th Annual Design Automation Conference, ACM, New York, pp. 250–253 2009Google Scholar
  5. 5.
    Tensilica, Xtensa customizable processor. http://www.tensilica.com
  6. 6.
    M. Yourst, PTLsim: a cycle accurate full system x86–64 microarchitectural simulator, in Performance Analysis of Systems and Software, ISPASS 2007. IEEE International Symposium on, pp. 23–34 Aprl 2007Google Scholar
  7. 7.
    ARM, RealView ARMulator ISS. http://www.arm.com
  8. 8.
    R. Srinivasan, J. Cook, O. Lubeck, Performance modeling using monte carlo simulation, Comput. Archit. Lett. 5, 38–41 (2006)Google Scholar
  9. 9.
    H. Javaid, A. Ignjatovic, S. Parameswaran, Rapid design space exploration of application specific heterogeneous pipelined multiprocessor systems. Trans. Comp.-Aided Des. Integ. Cir. Sys. 29, 1777–1789 (2010)CrossRefGoogle Scholar
  10. 10.
    M.S. Haque, J. Peddersen, A. Janapsatya, S. Parameswaran, Dew: a fast level 1 cache simulation approach for embedded processors with fifo replacement policy, in DATE ’10: Proceedings of the conference on Design, automation and test in, Europe, 2010Google Scholar
  11. 11.
    J. Edler, M.D. Hill, Dinero iv trace-driven uniprocessor cache simulator. http://www.cs.wisc.edu/markhill/DineroIV/, 2004
  12. 12.
    N. Tojo, N. Togawa, M. Yanagisawa, T. Ohtsuki, Exact and fast l1 cache simulation for embedded systems, in ASP-DAC ’09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, IEEE Press, Piscataway, pp. 817–822 2009Google Scholar
  13. 13.
    L. Singleton, C. Poellabauer, K. Schwan, Monitoring of cache miss rates for accurate dynamic voltage and frequency scaling, in Proceedings of the Multimedia Computing and Networking Conference (MMCN), 2005Google Scholar
  14. 14.
    B.C. Lee, D.M. Brooks, Accurate and efficient regression modeling for microarchitectural performance and power prediction, in ASPLOS-XII: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, New York, pp. 185–194 2006Google Scholar
  15. 15.
    P. Joseph, K. Vaswani, M. Thazhuthaveetil, Construction and use of linear regression models for processor performance analysis, in Proceedings of the High-Performance Computer Architecture, The Twelfth International Symposium on, pp. 99–108 2006Google Scholar
  16. 16.
    T.S. Karkhanis, J.E. Smith, A first-order superscalar processor model. SIGARCH Comput. Archit. News 32(2), 338 (2004)CrossRefGoogle Scholar
  17. 17.
    A. Ghamarian, M. Geilen, S. Stuijk, T. Basten, A. Moonen, M. Bekooij, B. Theelen, M. Mousavi, Throughput analysis of synchronous data flow graphs, in Proceedings of the Application of Concurrency to System Design, ACSD 2006. Sixth International Conference on, pp. 25–36 june 2006Google Scholar
  18. 18.
    A. Ghamarian, M. Geilen, T. Basten, S. Stuijk, Parametric throughput analysis of synchronous data flow graphs, in Proceedings of the Design, Automation and Test in Europe, DATE ’08, pp. 116–121 March 2008Google Scholar
  19. 19.
    Tensilica, Flix: fast relief for performance-hungry embedded applications. http://www.tensilica.com/
  20. 20.
    Tensilica, XPRES generated specialized operations. http://www.tensilica.com/
  21. 21.
    H. Javaid, A. Ignjatovic, S. Parameswaran, Fidelity metrics for estimation models, in Proceedings of the Computer-Aided Design (ICCAD), IEEE/ACM International Conference on, pp. 1–8 Nov 2010Google Scholar

Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.School of Computer Science and EngineeringUniversity of New South WalesKensingtonAustralia

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