Abstract
This chapter focuses on analytical models and estimation methods for three performance metrics (execution time, latency and throughput) of pipelined MPSoCs to speed up their design space exploration process.
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Notes
- 1.
Note that in real-time, the input data to first processor will be available at the rate equal to throughput of the pipelined MPSoC. In such a scenario, number of FIFO buffers between the first processor and critical processor will not affect the latency of the pipelined MPSoC because the input data will not be available to the first processor in advance. Hence, the second factor will not contribute to the latency of a real-time pipelined MPSoC.
- 2.
Fidelity measures the correlation between the ordering of the actual and estimated values to quantify the similarity between the trends of actual and estimated values. A value close to 1 means that an analytical model has high fidelity. \(FM_{\rho }\) metric from [21] is used to compute fidelity due to its lower computational complexity.
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Javaid, H., Parameswaran, S. (2014). Performance Estimation of Pipelined MPSoCs. In: Pipelined Multiprocessor System-on-Chip for Multimedia. Springer, Cham. https://doi.org/10.1007/978-3-319-01113-4_4
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