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Low-Power Design of Hybrid Instruction Cache Based on Branch Prediction and Drowsy Cache

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 246)

Abstract

In the design of modern high-performance embedded processors, Branch prediction and larger capacity instruction cache greatly improves the performance of processors. They also consume a larger proportion of total power consumption of processors at the same time. There are many methods to reduce their power consumption. However, there is few method of combining them to reduce the power consumption. Based on these two technologies having a similar structure, this paper presents a hybrid cache structure of combining them to a new structure named B-Cache. By the method, we reduce the number of Comparisons of tag or PC. And based on spatial locality of instruction cache, we propose the method to reduce the number of tag comparison of instruction cache. By the experiments, we found this method compared with the common method of two-port BTB used to wake up cache line on demand can significantly improve the performance and reduce the power consumption of processors.

Keywords

Branch prediction Instruction Cache B-Cache Tag 

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Copyright information

© Springer International Publishing Switzerland 2014

Authors and Affiliations

  1. 1.Xi’an Microelectronics Technology InstituteXianChina

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