Skip to main content
SpringerLink
Log in

Modern MOS-Based Power Device Technologies in Integrated Circuits

  • Chapter
  • First Online:
Lateral Power Transistors in Integrated Circuits

Part of the book series: Power Systems ((POWSYS))

  • 1410 Accesses

Abstract

The state-of-the-art of semiconductor device technology for LDMOS transistors in integrated circuits is introduced in this chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. J. Bardeen, W.H. Brattain, The transistor, a semi-conductor triode. Phys. Rev. 74(2), 230–231 (1947)

    Google Scholar 

  2. W. Shockley, The theory of p–n junctions in semiconductors and p–n junction transistors. Bell Syst. Tech. J. 28(4), 435–489 (1949)

    Article  Google Scholar 

  3. W.J. Pietenpol, R.S. Ohl, Characteristics of Silicon Transistors, in Conference on Electron Devices, Ann Arbor, USA (1950)

    Google Scholar 

  4. G.K. Teal, E. Buehler, Growth of silicon single crystals and of single crystal p–n junctions. Phys. Rev. 87, 190 (1952)

    Google Scholar 

  5. J.A. Hoerni, Planar silicon transistors and diodes. IRE Trans. Electron Devices 8, 178 (1961)

    Article  Google Scholar 

  6. R.N. Noyce, Semiconductor Device-and-Lead Structure. USA Patent 2,981,877, 25 April 1959

    Google Scholar 

  7. J.E. Lilienfeld, Method and Apparatus for Controlling Electric Circuits. USA Patent 1,745,175, 28 Jan 1930

    Google Scholar 

  8. O. Heil, Improvements in or Relating Amplifiers or Other Control Arrangements. UK Patent 439,457, 2 March 1934

    Google Scholar 

  9. M.M. Atalla, E. Tannenbaum, E.J. Scheibner, Stabilization of silicon surfaces by thermally grown oxides. Bell Labs Tech. J. 38(3), 749–783 (1959)

    Article  Google Scholar 

  10. D. Kahng, M.M. Atalla, Silicon–silicon dioxide field induced surface device, in Solid State Device Research Conference, Pittsburgh, USA 1960

    Google Scholar 

  11. W.F. Brinkman, D.E. Haggan, W.W. Troutman, A history of the invention of the transistor and where it will lead us. IEEE J. Solid-State Circuits 32(12), 1858–1865 (1997)

    Article  Google Scholar 

  12. H.J. Sigg, G.D. Vendelin, T.P. Cauge, J. Kocsis, D-MOS transistor for microwave applications. IEEE Trans. Electron Devices 9(1), 45–53 (1972)

    Article  Google Scholar 

  13. J.A. Appels, H.M.S. Vaes, High voltage thin layer devices, in International Electron Devices Meeting, Washington, USA, 1979

    Google Scholar 

  14. S. Colak, Effects of drift region parameters on the static properties of power LDMOST. IEEE Trans. Electron Devices ED-28(12), 1455–1466 (1981)

    Google Scholar 

  15. V.A.K. Temple, Junction termination extension (JTE), A new technique for increasing avalanche breakdown voltage and controlling surface electric fields in P-N junctions, in International Electron Devices Meeting, Washington, USA, 1977

    Google Scholar 

  16. O. Ishakawa, E. Hideya, A high-power high-gain VD-MOSFET operating at 900 MHz. IEEE Trans. Electron Devices ED-34(5), 1157–1162 (1987)

    Google Scholar 

  17. A. Wood, C. Dragon, W. Burger, High performance silicon LDMOS technology for 2 GHz RF power amplifier applications, in International Electron Device Meeting, San Francisco, USA, 1996

    Google Scholar 

  18. G. Deboy, M. März, J.-P. Stengl, H. Strack, J. Tihanyi, H. Weber, New generation of high voltage MOSFETs breaks the limit line of silicon, in International Electron Device Meeting, San Francisco, USA, 1998

    Google Scholar 

  19. S. Linder, Power Semiconductors, Lausanne (EFPL Press, Switzerland, 2006)

    Google Scholar 

  20. P. Moens, G. Van den bosch, D. Wojciechowski, F. Bauwens, H. De Vleeschouwer, F. De Pestel, Charge Trapping Effects and Interface State Generation in a 40 V Lateral Resurf pDMOS Transistor, in European Solid State Device Research Conference, Grenoble, France, 2005

    Google Scholar 

  21. A.W. Ludikhuize, A Review of RESURF Technology, International Symposium on Power Semiconductor Devices & ICs, pp. 11–18, 22–25 May 2000

    Google Scholar 

  22. M. Imam, Z. Hossain, M. Quddus, J. Adams, C. Hoggatt, T. Ishiguro, R. Nair, Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process. IEEE Trans. Electron Devices 50(7), 1697–1701 (2003)

    Article  Google Scholar 

  23. V.P. O’Neil, P.G. Alonas, Relation between oxide thickness and the breakdown voltage of a planar junction with field relief electrode. IEEE Trans. Electron Devices ED-26(7), 1098–1100 (1979)

    Google Scholar 

  24. Z. Parpia, C.A.T. Salama, Optimization of RESURF LDMOS transistors: an analytical approach. IEEE Trans. Electron Devices 37(3), 789–796 (1990)

    Article  Google Scholar 

  25. W. Fulop, Calculation of avalanche breakdwon of silicon p–n junctions. Solid-State Electron. 10, 39–43 (1967)

    Article  Google Scholar 

  26. M.M.-H. Iqbal, F. Udrea, E. Napoli, On the static performance of the RESURF LDMOSFETs for power ICs, in International Symposium of Power Semiconductor Devices & ICs, Barcelona, Spain, 2009

    Google Scholar 

  27. K. Chen, C. Chen, The foundry perspective on integrated power technologies, in International Symposium on Semiconductor Devices & ICs, Barcelona, Spain, 2009

    Google Scholar 

  28. S. Pendharkar, R. Pan, T. Tamura, B. Todd, T. Efland, 7 to 30 V state-of-the-art power device implementation in 0.25 µm LBC7 BiCMOS-DMOS process technology, in International Symposium on Power Semiconductor Devices and ICs, Kitayushu, Japan, 2004

    Google Scholar 

  29. D. Riccardi, A. Causio, I. Filippi, A. Paleari, L.V.A. Pregnolato, P. Galbiati, C. Contiero, BCD8 from 7 V to 70 V: a new 0.18 µm technology platform to address the evolution of applications towards smart power ICs with high logic contents, in International Symposium on Power Semiconductor Devices and ICs, Jeju, Korea, 2007

    Google Scholar 

  30. R. Rudolf, C. Wagner, L. O’Riain, K.-H. Gebhardt, B. Kuhn-Heinricht, B. von Ehrenwall, A. von Ehrenwall, M. Strasser, M. Stecher, U. Glaser, S. Aresu, P. Kuepper, A. Mayerhofer, Automotive 130 nm smart-power-technology including embedded flash functionality, in International Symposium on Power Semiconductor Devices and ICs, San Diego, CA, USA, 2011

    Google Scholar 

  31. Y.-S. Pang, Dependence of electrical characteristics of improved BCD nLDMOS on process and structural parameters. J. Korean Phys. Soc. 59(2), 416–420 (2011)

    Google Scholar 

  32. K. Shirai, K. Yonemura, K. Watanabe, K. Kimura, Ultra-low on-resistance LDMOS implementation in 0.13 µm CD and BiCD process technologies for analog power IC’s, in International Symposium on Power Semiconductor Devices and ICs, Barcelona, Spain, 2009

    Google Scholar 

  33. I.-Y. Park, Y.-K. Choi, K.-Y. Ko, C.-J. Yoon, B.-K. Jun, M.-Y. Kim, H.-C. Lim, N.-J. Kim und K.-D. Yoo, BD180—a new 0.18 µm BCD (Bipolar-CMOS-DMOS) technology from 7 V to 60 V, in International Symposium on Power Semiconductor Devices and ICs, Orlando, FL, USA, 2008

    Google Scholar 

  34. K.-Y. Ko, I.-L. Park, Choi Y-K, C.-J. Yoon, J.-H. Moon, K.-M. Park, H.-C. Lim, S.-Y. Park, N.-J. Kim, K.-D. Yoo, L. N. Hutter, BD180LV—0.18 µm BCD technology with best-in-class LDMOS from 7 V to 30 V, in International Symposium on Power Semiconductor Devices and ICs, Hiroshima, Japan, 2010

    Google Scholar 

  35. Y.-K. Choi, I.-Y. Park, H.-C. Lim, M.-Y. Kim, C.-J. Yoon, N.-J. Kim, K.-D. Yoo, L. N. Hutter, A versatile 30 V analog CMOS process in a 0.18 µm technology for power management applications, in International Symposium on Power Semiconductor Devices and ICs, San Diego, CA, USA, 2011

    Google Scholar 

  36. X-FAB, 0.18 micron modular analog mixed hv technology, http://www.xfab.com/de/technologien/cmos/. [Zugriff am 31st May 2014]

  37. X-FAB, 0.35 Micron modular analog mixed signal technology with RF capability and HV extensions, http://www.xfab.com/de/technologien/cmos/. [Zugriff am 31st May 2014]

  38. R. Minixhofer, N. Feilchenfeld, M. Knaipp, G. Röhrer, J. M. Park, M. Zierak, H. Enichlmair, M. Levy, B. Loeffler, D. Hershberger, F. Unterleitner, M. Gautsch, K. Chatty, Y. Shi, W. Posch, E. Seebacher, M. Schrems, J. Dunn, D. Harame, A 120 V 180 nm high voltage CMOS smart power technology for system-on-chip integration, in International Symposium on Power Semiconductor Devices and ICs, Hiroshima, Japan, 2010

    Google Scholar 

  39. F. De Pestel, P. Moens, H. Hakim, K. De Vleeschouwer, K. Reynders, T. Colpaert, P. Colson, P. Coppens, S. Boonen, D. Dolognesi, M. Tack, Development of a robust 50 V 0.35 µm based smart power technology using trench isolation, in International Symposium on Power Semiconductor Devices and ICs, Cambridge, UK, 2003

    Google Scholar 

  40. Z. Lee, R. Zwingman, J. Zheng, W. Cai, P. Hurwitz, M. Racanelli, A Modular 0.18 um analog/RFCMOS technology comprising 32 GHz FT RF-LDMOS and 40 V complementary MOSFET devices, in Bipolar/BiCMOS Circuits and Technology Meeting, Maastricht, Netherlands, 2006

    Google Scholar 

  41. V. Parthasarathy, R. Zhu, V. Khemka, T. Roggenbauer, A. Bose, P. Hui, P. Rodriquez, J. Nivison, D. Collins, Z. Wu, I. Puchades, M. Butner, A 0.25 µm CMOS based 70 V smart power technology with deep trench for high-voltage isolation, in International Electron Devices Meeting, San Francisco, CA, USA, 2002

    Google Scholar 

  42. V. Parthasarathy, R. Zhu, V. Khemka, T. Roggenbauer, A. Bose, P. Hui, P. Rodriquez, J. Nivison, D. Collins, Z. Wu, I. Puchades, M. Butner, A 0.25 µm CMOS based 70 V smart power technology with deep trench for high-voltage isolation, in International Electron Devices Meeting, San Francisco, USA, 2002

    Google Scholar 

  43. Z. Hossain, T. Ishiguro, L. Tu, H. Corleto, F. Kuramae, R. Nair, Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor, in International Symposium on Power Semiconductor Devices and ICs, Kitakyushu, Japan, 2004

    Google Scholar 

  44. A.S. Chen, A. Shafi, R.W. Busse, R. Orr, R.H. Y. Lo, Molding compounds for high breakdown voltage applications on power ic semiconductors, in Proceedings of Electronic Components and Technology Conference, San Jose, California, 1997

    Google Scholar 

  45. J.W. Osenbach, W.R. Knolle, Semi-insulating silicon nitride (SinSiN) as a resistive field shield. IEEE Trans. Electron Devices 37(6), 1522–1528 (1990)

    Article  Google Scholar 

  46. Z. Hossain, I. Mohamed, J. Fultonm, M. Tanaka, Double-resurf 700 V N-channel LDMOS with best-in-class on-resistance, in International Symposium on Semiconductor Devices and ICs, Santa Fe, NM, USA, 2002

    Google Scholar 

  47. D.R. Disney, A.K. Paul, M. Darwish, R. Basecki, V. Rumennik, A new 800 V lateral MOSFET with dual conduction paths, in International Symposium on Power Semiconductor Devices and ICs, Osaka, Japan, 2001

    Google Scholar 

  48. A.W. Ludikhuize, J.A. van der Pol, A. Heringa, A. Padiy, E.R. Ooms, P. van Kessel, G.J.J. Hessels, B. van Velzen, H. van der Vlist, J.H.H.A. Egbers, M. Stoutjesdijk, Extended (180 V) voltage in 0.6 um thin-layer silicon-on insulator BCD-technology on 1 um BOX for display, automotive and consumer applications, in International Symposium on Power Semiconductors and ICs, Santa Fe, USA, 2002

    Google Scholar 

  49. A.W. Ludikhuize, A versatile 700–1200 V IC process for analog and switching applications. IEEE Trans. Electron Devices 18(7), 1582–1589 (1991)

    Article  Google Scholar 

  50. K. Kinoshita, Y. Kawaguchi, T. Sano, A. Nakagawa, 20 V LDMOS optimized for high drain current condition—which is better, n-epi or p-epi?, in International Symposium on Power Semiconductor Devices and ICs, Toronto, Canada, 1999

    Google Scholar 

  51. H. Wang, H.P.E. Xu, W.T. Ng, K. Fukumoto, K. Abe, A. Ishikawa, Y. Furukawa, H. Imai, T. Naito, N. Sato, K. Sakai, S. Tamura, K. Takasuka, A novel orthogonal gate EDMOS transistor with improved dv/dt capability and figure of merit (FOM). IEEE Electron Device Lett. 29(12), 1386–1388 (2008)

    Article  Google Scholar 

  52. V. Khemka, V. Parthasarathy, R. Zhu, A. Bose, T. Roggenbauer, Floating RESURF (FRESURF) LDMOSFET devices with breakthrough BVdss-Rdson, in International Symposium on Power Semiconductor Devices and ICs, Kitakyushu, Japan, 2004

    Google Scholar 

  53. V. Parthasarathy, R. Zhu, W. Peterson, M. Zunino, R. Baird, A 33 V, 0.25 mOhm-cm2 n-channel LDMOS in a 0.65 µm smart power technology for 20–30 V applications, in International Symposium on Power Semiconductor Devices and ICs, Kyoto, Japan, 1998

    Google Scholar 

  54. K. Sakamoto, M. Shiraishi, T. Iwasaki, Low on-resistance and low feedback charge, lateral power MOSFETs with multi-drain regions for high-efficient DC/DC converters, in International Symposium on Power Semiconductor Devices and ICs, Santa Fe, USA, 2002

    Google Scholar 

  55. S.T. Kong, P. Stribley, C. Lee, M. Ong, Integration of 100 V LDMOS devices in 0.35 µm CMOS technology, in International Symposium on Power Semiconductor Devices and ICs, San Diego, USA, 2011

    Google Scholar 

  56. N. Klein, S. Levin, G. Fleishon, S. Levy, A. Eyal und S. Shapira, Device Design Tradeoffs for 55 V LDMOS Driver Embedded in 0.18 Micron Platform, in IEEE Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, 2008

    Google Scholar 

  57. T. Efland, S. Malhi, W. Bailey, O.K. Kwon, W.T. Ng, M. Torreno, S. Keller, An optimized RESURF LDMOS power device module compatible with advanced logic processes, in International Electron Devices Meeting, San Francisco, USA, 1992

    Google Scholar 

  58. A.W. Ludikhuize, Self-aligned and shielded-RESURF LDMOS for dense 20 V power IC’s, in International Symposium on Power Semiconductor Devices and ICs, Toronto, Canada, 1999

    Google Scholar 

  59. W. Chen, B. Zhang, Z. Li, A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC. Microelectron. J. 37(7), 574–578 (2006)

    Article  Google Scholar 

  60. I. Cortes, P. Fernandez-Martinez, D. Flores, S. Hidalgo, J. Rebollo, Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates. Semiconduct. Sci. Technol. 23, 015009 (2008)

    Article  Google Scholar 

  61. T. Erlbacher, A.J. Bauer, L. Frey, Significant on-resistance reduction of LDMOS devices by intermitted trench gates integration. IEEE Trans. Electron Devices 59, 3470–3476 (2012)

    Article  Google Scholar 

  62. M.A. Amberetu, C.A.T. Salama, 150-V class superjunction power LDMOS transistor switch on SOI, in International Symposium on Power Semiconductors and ICs, Santa Fe, USA, 2002

    Google Scholar 

  63. M.J. Kumar, R. Sithanandam, Extended-p+ stepped gate LDMOS for improved performance. IEEE Trans. Electron Device 57(7), 1719–1724 (2010)

    Article  Google Scholar 

  64. I. Cortés, J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo, A numerical study of field plate configurations in RF SOI LDMOS transistors. Solid-State Electron. 50, 155–163 (2006)

    Article  Google Scholar 

  65. P.H. Wilson, A novel trench gate LDMOS for RF applications, in International Crimean Conference on Microwave and Telecommunication Technology, Sevastopol, Ukraine, 2003

    Google Scholar 

  66. N.R. Mohapatra, H. Ruecker, K.E. Ehwald, R. Sorge, R. Barth, P. Schley, D. Schmidt, H.E. Wulf, A complementary RF-LDMOS architecture compatible with 0.13 µm CMOS technology, in International Symposium on Power Semiconductor Devices and ICs, Naples, Italy, 2006

    Google Scholar 

  67. S. Matsumoto, M. Mino, Impact of the pattern layout on radio-frequency performance of thin-film SOI power MOSFETs, in International Symposium on Power Semiconductor Devices and ICs, Kitakyusha, Japan, 2004

    Google Scholar 

  68. A. Mai, H. Ruecker, R. Sorge, D. Schmidt, C. Wipf, Cost-effective integration of RF-LDMOS transistors in 0.13 µm CMOS technology, in Silicon Monolithic Integrated Circuits in RF Systems, San Diego, USA, 2009

    Google Scholar 

  69. R. Sorge, A. Fischer, A. Mai, P. Schley, J. Schmidt, C. Wipf, T. Mausolf, R. Pliquett, R. Barth, K.E. Ehwald, Complementary RF LDMOS module for 12 V DC/DC converter and 6 GHz power applications, in Silicon Monolithic Integrated Circuits in RF Systems, Phoenix, USA, 2011

    Google Scholar 

  70. D. Muller, A. Giry, D. Pache, J. Mourier, B. Szelag, A. Monroy, Architecture optimization of an N-channel LDMOS device dedicated to RF-power applications, in International Symposium on Power Semiconductor Devices and ICs, Santa Barbara, USA, 2005

    Google Scholar 

  71. B. Szelag, D. Muller, J. Mourier, F. Judong, A. Giry, D. Pache, A. Monroy, M. Roche, NLDMOS RF optimzation guidelines for wireless power amplifier applications, in Bipolar/BiCMOS Circuits and Technology Meeting, Santa Barbara, USA, 2005

    Google Scholar 

  72. B. Szelag, H. Baudry, D. Muller, A. Giry, D. Lenoble, B. Reynard, D. Pache, A. Monroy, Integration and optimization of a high performance RF lateral DMOS in an advanced BiCMOS technology, in European Solid-State Device Research Conference, Estoril, Portugal, 2003

    Google Scholar 

  73. D. Muller, A. Giry, F. Judong, C. Rossato, F. Blanchet, B. Szelag, A. Monroy, R. Sommet, D. Pache, O. Noblanc, High-performance 15-V Novel LDMOS transistor architecture in a 0.25-µm BiCMOS process for RF-power applications. IEEE Trans. Electron Devices 54(4), 861–868 (2007)

    Article  Google Scholar 

  74. K.E. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Ruecker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H.E. Wulf, R. Pazirandeh, N. Ilkov, High performance RF LDMOS transistors with 5 nm gate oxide in a 0.25 µm SiGe:C BiCMOS technology, in International Electron Devices Meeting, Washington, USA, 2001

    Google Scholar 

  75. O. Bengtsson, A. Litwin, J. Olsson, Small-signal and power evaluation of novel BiCMOS-compatible short-channel LDMOS technology. Trans. Microw. Theory Techn. 51(3), 1052–1056 (2003)

    Article  Google Scholar 

  76. J.-P. Colinge, Fully-depleted SOI CMOS for analog applications. IEEE Trans. Electron Devices 45(5), 1010–1016 (1998)

    Article  Google Scholar 

  77. G.K. Celler, S. Cristoloveanu, Frontiers of silicon-on-insulator. J. Appl. Phys. 93(9), 4955–4978 (2003)

    Google Scholar 

  78. S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, R. Pinker, Realization of high breakdown voltage (>700 V) in thin SOI devices, in International Symposium on Power Semiconductor Devices and ICs, Baltimore, USA, 1991

    Google Scholar 

  79. S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S. Mukherjee, H. Pein, Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors, in International Symposium on Power Semiconductor Devices and ICs, Monterey, USA, 1993

    Google Scholar 

  80. I.-J. Kim, S. Matsumoto, T. Sakai, T. Yachi, Analytical approach to breakdown voltages in thin-film SOI power MOSFETs. Solid-State Electron. 39(1), 95–100 (1996)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Lehrstuhl für Elektronische Bauelemente, Universität Erlangen-Nürnberg, Erlangen, Germany

    Tobias Erlbacher

Authors
  1. Tobias Erlbacher
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Tobias Erlbacher .

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Erlbacher, T. (2014). Modern MOS-Based Power Device Technologies in Integrated Circuits. In: Lateral Power Transistors in Integrated Circuits. Power Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-00500-3_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-00500-3_5

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-00499-0

  • Online ISBN: 978-3-319-00500-3

  • eBook Packages: EnergyEnergy (R0)

Publish with us

Policies and ethics

Search

Navigation