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Part of the book series: Lehr- und Handbücher der Ingenieurwissenschaften ((LHI,volume 31))

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Zusammenfassung

Es sollen in diesem Abschnitt einige Ergänzungen angegeben werden zur elementaren Vereinfachungsmethode mit dem Karnaugh-Diagramm, wie sie in Kapitel I, Abschnitt 2.5, eingeführt wurde.

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Literaturverzeichnis zu Kapitel VII

Allgemeine Literatur

  1. Hill, F. J., and Peterson, G. R., Introduction to Switching Theory and Logical Design (John Wiley and Sons, Inc., New York 1968 ).

    Google Scholar 

  2. Mccluskey, E. J., Introduction to the Theory of Switching Circuits ( McGraw-Hill Book Co., New York 1965 ).

    Google Scholar 

  3. Caldwell, S. H., Switching Circuits and Logical Design (John Wiley and Sons, Inc., New York 1958 ).

    Google Scholar 

  4. Deutsche Übersetzung: Der logische Entwurf von Schaltkreisen ( Oldenbourg-Verlag, München 1964 ).

    Google Scholar 

  5. Lewin, D., Logical Design of Switching Circuits (Thomas Nelson and Sons Ltd, London 1968). -

    Google Scholar 

  6. Perrin, J. P., Denouette, M. and Daclin, E., Systèmes Logiques, Tome 1: Systèmes Combinatoires, Introduction aux systèmes séquentiels; Tome 2: Systèmes séquentiels (Dunod, Paris 1967 ).

    Google Scholar 

  7. Naslin, P., Circuits logiques et automatismes à séquences, 3. Aufl. (Dunod, Paris 1970 ).

    Google Scholar 

  8. Maley, G. A. and Earle, J., The Logic Design of Transistor Digital Computers (Prentice-Hall, Englewood Cliffs, N. J. 1963 ).

    Google Scholar 

  9. Miller, R. E., Switching Theory, Vol. I.: Combinational Circuits, Voll. II.: Sequential Circuits and Machines ( John Wiley and Sons, New York 1965 ).

    Google Scholar 

  10. Marcus, M. P., Switching Circuits for Engineers, 2. Aufl. (Prentice Hall, Englewood Cliffs, N. J. 1967 ).

    Google Scholar 

  11. Florine, J., La synthèse des machines logiques et son automatisation ( Presses académiques européennes, Bruxelles 1964 ).

    Google Scholar 

  12. Oberman, R. M. M., Disciplines in Combinational and Sequential Circuit Design ( McGraw-Hill Book Co., New York 1970 ).

    Google Scholar 

  13. Unger, S. H., Asynchronous Sequential Switching Circuits (John Wiley and Sons, Inc., New York 1969 ).

    Google Scholar 

Literatur zu Spezialproblemen

  1. Mccluskey, E. J., JR., Minimization of Boolean Functions, Bell System Technical Journal 35, 1417–1444 (1956).

    Article  Google Scholar 

  2. Desarzens, P., Méthode pour la simplification automatique de systèmes logiques à sorties multiples, Agen-Mitteilungen Nr. 7, 11–18 (1967).

    Google Scholar 

  3. Davidson, E. S., An Algorithm forNandDecomposition of Combinational Switching Systems, Ieee Trans. on Computers C-18, 1098–1109 (1969).

    Google Scholar 

  4. Su, S. Y. and Nam, C. W., Computer-Aided Synthesis of Multiple-Output MultilevelNandNetworks with Fan-In and Fan-Out Constraints, Ieee Trans. on Computers C-20, 1445–1455 (1971).

    Google Scholar 

  5. Schneider, P. R. and Dietmeyer, D. L., An Algorithm for Synthesis of Multiple-Output Combinational Logic, Ieee Trans. on Computers 17, 117–128 (1968).

    Article  Google Scholar 

  6. Davidson, E. S., and Metze, G., Comments on “An Algorithm for Synthesis of Multiple Output Combinational Logic”, Ieee Trans. on Computers C-17, 1091–1092 (1968).

    Google Scholar 

  7. Gimple, J. F., The Minimization of Tant-Networks, Ieee Trans. on Electronic Computers EC-16, 18–38 (1967).

    Google Scholar 

  8. Kou, Kyung Shik, A Minimization Technique for Tant Networks, Ieee Trans. on Computers C-20, 105–107 (1971).

    Google Scholar 

  9. Karp, R. M., Functional Decomposition and Switching Circuit Design, J. Soc. Ind. Appl. Math. 11, 291–335 (1963).

    Article  Google Scholar 

  10. Prather, R. E., On Tree Circuits, Ieee Trans. on Electronic Computers EC-14, 841851 (1965).

    Google Scholar 

  11. Hellermann, L., A Catalog of Three-Variable OR-Invert and And-Invert Logical Circuits, Ieee Trans. on Electronic Computers 12, 198–223 (1963).

    Article  Google Scholar 

  12. Smith, R. A., Minimal Three Variable Nor and Nand Logic Circuits, Ieee Trans. on Electronic Computers 14, 79–81 (1965).

    Article  Google Scholar 

  13. Baugh, C. R., Chandersekaran, C. S., Swee, R. S. and Muroga, S., Optimal Networks of Nor-Or Gates for Functions of Three Variables, Ieee Trans. on Computers 21, 153–160 (1972).

    Article  Google Scholar 

  14. Huffman, D. A., The Synthesis of Sequential Switching Circuits, J. of the Franklin Institute 257, 161–190, 275–303 (1954).

    Article  Google Scholar 

  15. Mange, J. D., Synthèse des machines séquentielles synchronisées, Systèmes logiques 4, 198–212 (1972).

    Google Scholar 

  16. Mealy, G. H., A Method for Synthesizing Sequential Circuits, Bell System Technical Journal 34, 1045–1079 (1955).

    Article  Google Scholar 

  17. Hartmanis, J., On the State Assignment Problem for Sequential Machines I, Ire Trans. on Electronic Computers 10, 157–165, (1961).

    Article  Google Scholar 

  18. Stearns, R. E., and Hartmanis, J., On the State Assignment Problem for Sequential Machines II, Ire Trans. on Electronic Computers 10, 593–603 (1961).

    Article  Google Scholar 

  19. Hartmanis, J., and Stearns, R. E. Algebraic Structure Theory of Sequential Machines, Prentice Hall, Englewood Cliffs, N. J. (1966).

    Google Scholar 

  20. Dolotta, T. A., and Mccluskey, E. J., The Coding of Internal States of Sequential Circuits, Ieee Trans. on Electronic Computers 13, 549–562 (1964).

    Article  Google Scholar 

  21. Weiner, P., and Smith, E. J., Optimalization of Reduced Dependencies for Synchronous Sequential Machines, Ire Trans. on Electronic Computers 16, 835–847 (1967).

    Article  Google Scholar 

  22. Weiner, P., and Dolotta, T. A., Mixed Memory Type Realizations of Sequential Machines, Ieee Trans. on Computers 18, 272–277 (1969).

    Article  Google Scholar 

  23. Curtis, H. A., Systematic Procedures for Realizing Synchronous Machines Using Flip-Flop Memory, Ieee Trans. on Computers, part I.: C-18, 1121–1127 (1969), part II.: C-19, 66–73 (1970).

    Google Scholar 

  24. Curtis, H. A., The Realization of Polylinear Sequential Circuits Using Flip-Flop Memory, Ieee Trans. on Computers 20, 87–94 (1971).

    Article  Google Scholar 

  25. Beizer, B., Towards a New Theory of Sequential Switching Networks, Ieee Trans. on Computers 19, 939–956 (1970).

    Article  Google Scholar 

  26. Mccluskey, E. J., and Unger, S. H., A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits, Ire Trans. on Electronic Computers 8, 439–440 (1959).

    Article  Google Scholar 

  27. Corn, M., and Even, S., The Design of Shift Register Generators for Finite Sequences, Ieee Trans. on Computers 18, 660–662 (1969).

    Google Scholar 

  28. Martin, R. L., Studies in Feedback-Shift-Register Synthesis of Sequential Machines, M. I. T. Research Monograph No 50 (M. I. T. Press, Cambridge, Mass., 1969 ).

    Google Scholar 

  29. Unger, S. H., Hazards and Delays in Asynchronous Sequential Switching Circuits, Ire Trans. on Circuit Theory 6, 12–25 (1959).

    Article  Google Scholar 

  30. TexasInstruments Inc., Mos-Array is Customprogrammabl, Electronics 30. März 1970, 133–134.

    Google Scholar 

  31. Gardner, P. L., Functional Memory and its Microprogramming Implications, Ieee Trans. on Computers, 20, 764–775 (1971).

    Article  Google Scholar 

  32. Mrazek, P., Characteristics and Applications of « Tri-State » IC’s, Application Note AN-45 of National Semiconductor Corporation, Santa Clara, Calif., July 1971.

    Google Scholar 

  33. Ikeno, N., Hashimoto, A., and Naito, K., A Table of Four-Variable MinimalNand Circuits, Electrical Communication Laboratory Technical Journal, Extra Issue No. 26 ( Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan, 1968 ).

    Google Scholar 

  34. Reyling, G., PlasEnhance Digital Processor Speed and Cut Component Count, Electronics August 8, 1974, 109–114.

    Google Scholar 

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Shah, A., Saglini, M., Weber, C. (1976). Einige Ergänzungen zur Logik. In: Integrierte Schaltungen in digitalen Systemen. Lehr- und Handbücher der Ingenieurwissenschaften, vol 31. Birkhäuser, Basel. https://doi.org/10.1007/978-3-0348-5938-7_7

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  • DOI: https://doi.org/10.1007/978-3-0348-5938-7_7

  • Publisher Name: Birkhäuser, Basel

  • Print ISBN: 978-3-0348-5939-4

  • Online ISBN: 978-3-0348-5938-7

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