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Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers

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Smart Card Research and Advanced Applications (CARDIS 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14530))

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Abstract

Model extraction is a growing concern for the security of AI systems. For deep neural network models, the architecture is the most important information an adversary aims to recover. Being a sequence of repeated computation blocks, neural network models deployed on edge-devices will generate distinctive side-channel leakages. The latter can be exploited to extract critical information when targeted platforms are physically accessible. By combining theoretical knowledge about deep learning practices and analysis of a widespread implementation library (ARM CMSIS-NN), our purpose is to answer this critical question: how far can we extract architecture information by simply examining an EM side-channel trace? For the first time, we propose an extraction methodology for traditional MLP and CNN models running on a high-end 32-bit microcontroller (Cortex-M7) that relies only on simple pattern recognition analysis. Despite few challenging cases, we claim that, contrary to parameters extraction, the complexity of the attack is relatively low and we highlight the urgent need for practicable protections that could fit the strong memory and latency requirements of such platforms.

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Notes

  1. 1.

    https://gitlab.emse.fr/securityml/model-architecture-extraction.

  2. 2.

    With \(P=0\), borders are not considered and the output tensor is shorter.

  3. 3.

    \(S=1\) is the standard default sliding, one element at a time.

  4. 4.

    https://www.tensorflow.org/lite/microcontrollers.

  5. 5.

    https://www.st.com/en/embedded-software/x-cube-ai.html.

  6. 6.

    In [20], authors consider 4 variants of AlexNet, Inceptionv3, ResNet-50 and 101, for a total of 16 architectures.

  7. 7.

    http://yann.lecun.com/exdb/MNIST/.

  8. 8.

    https://www.cs.toronto.edu/~kriz/cifar.html.

  9. 9.

    Raw traces are available in the public repository.

  10. 10.

    Obviously, we expect that the size of the inputs feeding the model is known by the adversary (e.g., \(28\times 28\) for MNIST and \(32\times 32\times 3\) for Cifar-10).

  11. 11.

    Equivalent functions are available for non-squared input tensor.

  12. 12.

    Obviously, if the dense layer had x4.5 more neurons, MAC complexity between dense and conv. would be equal but having a too large number of neurons (i.e. trainable parameters) for dense layers is usually unsuitable with classical overfitting issues.

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Acknowledgements

This work is supported by (CEA-Leti) the EU project InSecTT (ECSEL JU 876038) and by ANR (Fr) in the framework Investissements d’avenir program (ANR-10-AIRT-05, irtnanoelec); and (Mines Saint-Etienne) by ANR PICTURE program (AAPG2020). This work benefited from the French Jean Zay supercomputer with the AI dynamic access program.

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Correspondence to Pierre-Alain Moëllic .

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Joud, R., Moëllic, PA., Pontié, S., Rigaud, JB. (2024). Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers. In: Bhasin, S., Roche, T. (eds) Smart Card Research and Advanced Applications. CARDIS 2023. Lecture Notes in Computer Science, vol 14530. Springer, Cham. https://doi.org/10.1007/978-3-031-54409-5_13

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