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Memory Checking for Parallel RAMs

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Theory of Cryptography (TCC 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 14370))

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Abstract

When outsourcing a database to an untrusted remote server, one might want to verify the integrity of contents while accessing it. To solve this, Blum et al. [FOCS ‘91] propose the notion of memory checking. Memory checking allows a user to run a RAM program on a remote server, with the ability to verify integrity of the storage with small local storage.

In this work, we define and initiate the formal study of memory checking for Parallel RAMs (PRAMs). The parallel RAM model is very expressive and captures many modern architectures such as multi-core architectures and cloud clusters. When multiple clients run a PRAM algorithm on a shared remote server, it is possible that there are concurrency issues that cause inconsistencies. Therefore, integrity verification is even more desirable property in this setting.

Assuming only the existence of one-way functions, we construct an online memory checker (one that reports faults as soon as they occur) for PRAMs with \(O(\log N)\) simulation overhead in both work and depth. In addition, we construct an offline memory checker (one that reports faults only after a long sequence of operations) with amortized O(1) simulation overhead in both work and depth. Our constructions match the best known simulation overhead of the memory checkers in the RAM settings. As an application of our parallel memory checking constructions, we additionally construct the first maliciously secure oblivious parallel RAM (OPRAM) with polylogarithmic overhead.

The author was supported in part by DARPA under Agreement No. HR00112020023, an NSF grant CNS-2154149, a grant from the MIT-IBM Watson AI, a grant from Analog Devices, a Microsoft Trustworthy AI grant, and a Thornton Family Faculty Research Innovation Fellowship from MIT. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the United States Government or DARPA.

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Notes

  1. 1.

    Arasu et al. [2] ultimately instantiate the algorithm of Blum et al. [6] with pseudorandom functions.

  2. 2.

    If there is a rule for conflict resolution that can be easily verified (e.g. the CPU with the highest priority wins, CPU with the maximum or minimum value write wins, etc.), then that can also be verified here.

  3. 3.

    If there is a rule for conflict resolution that can be easily verified (e.g. the CPU with the lowest number wins), then that can also be verified here.

References

  1. Ajtai, M.: The invasiveness of off-line memory checking. In: 34th ACM STOC, pp. 504–513. ACM Press (2002). https://doi.org/10.1145/509907.509981

  2. Arasu, A., et al.: Concerto: a high concurrency key-value store with integrity. In: Proceedings of the 2017 ACM International Conference on Management of Data, pp. 251–266 (2017)

    Google Scholar 

  3. Asharov, G., Komargodski, I., Lin, W.K., Peserico, E., Shi, E.: Optimal oblivious parallel ram. In: Proceedings of the 2022 Annual ACM-SIAM Symposium on Discrete Algorithms (SODA), pp. 2459–2521. SIAM (2022)

    Google Scholar 

  4. Asharov, G., Komargodski, I., Lin, W.-K., Shi, E.: Oblivious RAM with Worst-Case logarithmic overhead. In: Malkin, T., Peikert, C. (eds.) CRYPTO 2021. LNCS, vol. 12828, pp. 610–640. Springer, Cham (2021). https://doi.org/10.1007/978-3-030-84259-8_21

    Chapter  Google Scholar 

  5. Bindschaedler, V., Naveed, M., Pan, X., Wang, X., Huang, Y.: Practicing oblivious access on cloud storage: the gap, the fallacy, and the new way forward. In: Ray, I., Li, N., Kruegel, C. (eds.) ACM CCS 2015, pp. 837–849. ACM Press (2015). https://doi.org/10.1145/2810103.2813649

  6. Blum, M., Evans, W.S., Gemmell, P., Kannan, S., Naor, M.: Checking the correctness of memories. In: 32nd FOCS, pp. 90–99. IEEE Computer Society Press (1991). https://doi.org/10.1109/SFCS.1991.185352

  7. Boyle, E., Chung, K.-M., Pass, R.: Oblivious parallel RAM and applications. In: Kushilevitz, E., Malkin, T. (eds.) TCC 2016. LNCS, vol. 9563, pp. 175–204. Springer, Heidelberg (2016). https://doi.org/10.1007/978-3-662-49099-0_7

    Chapter  Google Scholar 

  8. Chan, T.-H.H., Chung, K.-M., Shi, E.: On the depth of oblivious parallel RAM. In: Takagi, T., Peyrin, T. (eds.) ASIACRYPT 2017. LNCS, vol. 10624, pp. 567–597. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-70694-8_20

    Chapter  Google Scholar 

  9. Chan, T.-H.H., Guo, Y., Lin, W.-K., Shi, E.: Oblivious hashing revisited, and applications to asymptotically efficient ORAM and OPRAM. In: Takagi, T., Peyrin, T. (eds.) ASIACRYPT 2017. LNCS, vol. 10624, pp. 660–690. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-70694-8_23

    Chapter  Google Scholar 

  10. Hubert Chan, T.-H., Shi, E.: Circuit OPRAM: unifying statistically and computationally secure ORAMs and OPRAMs. In: Kalai, Y., Reyzin, L. (eds.) TCC 2017. LNCS, vol. 10678, pp. 72–107. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-70503-3_3

    Chapter  Google Scholar 

  11. Chen, B., Lin, H., Tessaro, S.: Oblivious parallel RAM: improved efficiency and generic constructions. In: Kushilevitz, E., Malkin, T. (eds.) TCC 2016. LNCS, vol. 9563, pp. 205–234. Springer, Heidelberg (2016). https://doi.org/10.1007/978-3-662-49099-0_8

    Chapter  Google Scholar 

  12. Chen, Y.C., Chow, S.S.M., Chung, K.M., Lai, R.W.F., Lin, W.K., Zhou, H.S.: Cryptography for parallel RAM from indistinguishability obfuscation. In: Sudan, M. (ed.) ITCS 2016, pp. 179–190. ACM (2016). https://doi.org/10.1145/2840728.2840769

  13. Connell, G.: Technology deep dive: Building a faster ORAM layer for enclaves. https://signal.org/blog/building-faster-oram/ (2022)

  14. Costan, V., Devadas, S.: Intel SGX explained. Cryptology ePrint Archive, Report 2016/086 (2016). https://eprint.iacr.org/2016/086

  15. Dauterman, E., Fang, V., Demertzis, I., Crooks, N., Popa, R.A.: Snoopy: surpassing the scalability bottleneck of oblivious storage. In: Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles, pp. 655–671 (2021)

    Google Scholar 

  16. Dolev, D., Strong, H.R.: Authenticated algorithms for byzantine agreement. SIAM J. Comput. 12(4), 656–666 (1983). https://doi.org/10.1137/0212045

  17. Dwork, C., Naor, M., Rothblum, G.N., Vaikuntanathan, V.: How efficient can memory checking be? In: Reingold, O. (ed.) TCC 2009. LNCS, vol. 5444, pp. 503–520. Springer, Heidelberg (2009). https://doi.org/10.1007/978-3-642-00457-5_30

    Chapter  Google Scholar 

  18. Fischer, M.J., Lynch, N.A.: A lower bound for the time to assure interactive consistency. Inf. Process. Lett. 14(4), 183–186 (1982). https://doi.org/10.1016/0020-0190(82)90033-3, https://www.sciencedirect.com/science/article/pii/0020019082900333

  19. Fischer, M.J., Lynch, N.A., Merritt, M.: Easy impossibility proofs for distributed consensus problems. Distrib. Comput. 1, 26–39 (1986)

    Article  MATH  Google Scholar 

  20. Fletcher, C.W., Dijk, M.V., Devadas, S.: A secure processor architecture for encrypted computation on untrusted programs. In: Proceedings of the Seventh ACM Workshop on Scalable Trusted Computing, pp. 3–8 (2012)

    Google Scholar 

  21. Fletcher, C.W., Ren, L., Kwon, A., van Dijk, M., Devadas, S.: Freecursive ORAM: [nearly] free recursion and integrity verification for position-based oblivious RAM. In: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems. p. 103–116. ASPLOS 2015, Association for Computing Machinery, New York, NY, USA (2015). https://doi.org/10.1145/2694344.2694353

  22. Gentry, C., Halevi, S., Jutla, C., Raykova, M.: Private database access with HE-over-ORAM architecture. In: Malkin, T., Kolesnikov, V., Lewko, A.B., Polychronakis, M. (eds.) ACNS 2015. LNCS, vol. 9092, pp. 172–191. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-28166-7_9

    Chapter  Google Scholar 

  23. Liu, C., Wang, X.S., Nayak, K., Huang, Y., Shi, E.: ObliVM: a programming framework for secure computation. In: 2015 IEEE Symposium on Security and Privacy, pp. 359–376. IEEE Computer Society Press (2015). https://doi.org/10.1109/SP.2015.29

  24. Lu, S., Ostrovsky, R.: Distributed oblivious RAM for secure two-party computation. In: Sahai, A. (ed.) TCC 2013. LNCS, vol. 7785, pp. 377–396. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-36594-2_22

    Chapter  Google Scholar 

  25. Lu, S., Ostrovsky, R.: Black-box parallel garbled RAM. In: Katz, J., Shacham, H. (eds.) CRYPTO 2017. LNCS, vol. 10402, pp. 66–92. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-63715-0_3

    Chapter  Google Scholar 

  26. Mathialagan, S., Vafa, N.: MacORAMa: Optimal oblivious RAM with integrity. In: To appear at CRYPTO 2023 (2023). https://eprint.iacr.org/2023/083

  27. Merkle, R.C.: A certified digital signature. In: Brassard, G. (ed.) CRYPTO 1989. LNCS, vol. 435, pp. 218–238. Springer, New York (1990). https://doi.org/10.1007/0-387-34805-0_21

    Chapter  Google Scholar 

  28. Naor, J., Naor, M.: Small-bias probability spaces: efficient constructions and applications. In: 22nd ACM STOC, pp. 213–223. ACM Press (1990). https://doi.org/10.1145/100216.100244

  29. Naor, M., Rothblum, G.N.: The complexity of online memory checking. J. ACM (JACM) 56(1), 1–46 (2009)

    Article  MathSciNet  MATH  Google Scholar 

  30. Papamanthou, C., Tamassia, R.: Optimal and parallel online memory checking. Cryptology ePrint Archive, Report 2011/102 (2011). https://eprint.iacr.org/2011/102

  31. Pease, M., Shostak, R., Lamport, L.: Reaching agreement in the presence of faults. J. ACM 27(2), 228–234 (1980). https://www.microsoft.com/en-us/research/publication/reaching-agreement-presence-faults/, 2005 Edsger W. Dijkstra Prize in Distributed Computing

  32. Ren, L., Fletcher, C.W., Yu, X., van Dijk, M., Devadas, S.: Integrity verification for path oblivious-RAM. In: 2013 IEEE High Performance Extreme Computing Conference (HPEC), pp. 1–6 (2013). https://doi.org/10.1109/HPEC.2013.6670339

  33. Shacham, H., Waters, B.: Compact proofs of retrievability. J. Cryptol. 26(3), 442–483 (2013). https://doi.org/10.1007/s00145-012-9129-2

    Article  MathSciNet  MATH  Google Scholar 

  34. Shi, E., Chan, T.-H.H., Stefanov, E., Li, M.: Oblivious RAM with O((logN)3) worst-case cost. In: Lee, D.H., Wang, X. (eds.) ASIACRYPT 2011. LNCS, vol. 7073, pp. 197–214. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-25385-0_11

    Chapter  Google Scholar 

  35. Wang, X.S., Huang, Y., Chan, T.H.H., shelat, A., Shi, E.: SCORAM: oblivious RAM for secure computation. In: Ahn, G.J., Yung, M., Li, N. (eds.) ACM CCS 2014, pp. 191–202. ACM Press (2014). https://doi.org/10.1145/2660267.2660365

  36. Zahur, S., et al.: Revisiting square-root ORAM: efficient random access in multi-party computation. In: 2016 IEEE Symposium on Security and Privacy, pp. 218–234. IEEE Computer Society Press (2016). https://doi.org/10.1109/SP.2016.21

  37. Mathialagan, S.: Memory checking for parallel RAMs. Cryptology ePrint Archive, Paper 2023/1703 (2023). https://eprint.iacr.org/2023/1703

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Acknowledgements

I would like to thank Vinod Vaikuntanathan and Virginia Vassilevska Williams for their enthusiasm and guidance, and for giving valuable feedback on this manuscript. I would like to thank Neekon Vafa and Wei Kai Lin for helpful discussions, and Rahul Ilango and Yael Kirkpatrick for giving feedback on the manuscript. I would like to thank Mohsen Ghaffari and Christoph Grunau for helpful discussions on PRAMs, and Nancy Lynch for helpful discussions about distributed systems and byzantine agreement. I would also like to thank the anonymous reviewers for their detailed comments on the manuscripts.

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  1. Massachusetts Institute of Technology, Cambridge, MA, USA

    Surya Mathialagan

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Correspondence to Surya Mathialagan .

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  1. Apple, Cupertino, CA, USA

    Guy Rothblum

  2. NTT Research, Sunnyvale, CA, USA

    Hoeteck Wee

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Mathialagan, S. (2023). Memory Checking for Parallel RAMs. In: Rothblum, G., Wee, H. (eds) Theory of Cryptography. TCC 2023. Lecture Notes in Computer Science, vol 14370. Springer, Cham. https://doi.org/10.1007/978-3-031-48618-0_15

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  • DOI: https://doi.org/10.1007/978-3-031-48618-0_15

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