Skip to main content
SpringerLink
Log in

Dynamic Single Flux Quantum Majority Gates

  • Chapter
  • First Online:
Single Flux Quantum Integrated Circuit Design

  • 66 Accesses

Abstract

Among the major issues in modern large scale rapid single flux quantum circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS electronic design automation (EDA) techniques, and extremely deep pipelines, which reduce the effective clock frequency. In this chapter, asynchronous dynamic SFQ majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large scale RSFQ circuits, thereby alleviating certain timing issues while reducing the required bias currents. Furthermore, asynchronous logic allows existing EDA tools to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in large scale RSFQ circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. K.K. Likharev, V.K. Semenov, RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. IEEE Trans. Appl. Supercond. 1(1), 3–28 (1991)

    Article  Google Scholar 

  2. O.A. Mukhanov, Energy-efficient single flux quantum technology. IEEE Trans. Appl. Supercond. 21(3), 760–769 (2011)

    Article  Google Scholar 

  3. S. Whiteley, E. Mlinar, G. Krylov, T. Jabbari, E.G. Friedman, J. Kawa, An SFQ digital circuit technology with fully-passive transmission line interconnect, in Proceedings of the Applied Superconductivity Conference (2020)

    Google Scholar 

  4. T. Jabbari, E.G. Friedman, Global interconnects in VLSI complexity single flux quantum systems, in Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop (2020), pp. 1–7

    Google Scholar 

  5. T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Repeater insertion in SFQ interconnect. IEEE Trans. Appl. Supercond. 30(8), 5400508 (2020)

    Google Scholar 

  6. W. Chen, A.V. Rylyakov, V. Patel, J.E. Lukens, K.K. Likharev, Rapid single flux quantum T-flip flop operating up to 770 GHz. IEEE Trans. Appl. Supercond. 9(2), 3212–3215 (1999)

    Article  Google Scholar 

  7. T. Jabbari, M. Bocko, E.G. Friedman, All-JJ logic based on bistable JJs. IEEE Trans. Appl. Supercond. 33(5), 1–7 (2023)

    Google Scholar 

  8. T. Jabbari, E.G. Friedman, Transmission lines in VLSI complexity single flux quantum systems, in Proceedings of the PhotonIcs and Electromagnetics Research Symposium (2023), pp. 1749–1759

    Google Scholar 

  9. R. Bairamkulov, T. Jabbari, E.G. Friedman, QuCTS – single flux quantum clock tree synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), 3346–3358 (2022)

    Article  Google Scholar 

  10. T. Jabbari, J. Kawa, E.G. Friedman, H-tree clock synthesis in RSFQ circuits, in Proceedings of the IEEE Baltic Electronics Conference (2020), pp. 1–5

    Google Scholar 

  11. T. Jabbari, G. Krylov, J Kawa, E.G. Friedman, Splitter trees in single flux quantum circuits. IEEE Trans. Appl. Supercond. 31(5), 1302606 (2021)

    Google Scholar 

  12. T. Jabbari, E.G. Friedman, Flux mitigation in wide superconductive striplines. IEEE Trans. Appl. Supercond. 32(3), 1–6 (2022)

    Article  Google Scholar 

  13. T. Jabbari, E.G. Friedman, Stripline topology for flux mitigation. IEEE Trans. Appl. Supercond. 335, 1–4 (2023)

    Google Scholar 

  14. T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Resonance effects in single flux quantum interconnect, in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (2020), pp. 1–5

    Google Scholar 

  15. T. Jabbari, E.G. Friedman, Surface inductance of superconductive striplines. IEEE Trans. Circuits Syst. II Express Briefs 69(6), 2952–2956 (2022)

    Google Scholar 

  16. G. Krylov, E.G. Friedman, Sense amplifier for spin-based cryogenic memory cells. IEEE Trans. Appl. Supercond. 29(5), 1–4 (2019). Art no. 1501804

    Google Scholar 

  17. D. Yohannes, S. Sarwana, S.K. Tolpygo, A. Sahu, Y.A. Polyakov, V.K. Semenov, Characterization of HYPRES’ 4.5 \(kA/cm^2\) & 8 \(kA/cm^2\)\(Nb/AlO_x/Nb\) fabrication processes. IEEE Trans. Appl. Supercond. 15(2), 90–93 (2005)

    Google Scholar 

  18. G. Krylov, E.G. Friedman, Partitioning RSFQ circuits for current recycling. IEEE Trans. Appl. Supercond. 31(5), 1–6 (2021)

    Article  Google Scholar 

  19. S.K. Tolpygo, V. Bolkhovsky, T.J. Weir, A. Wynn, D.E. Oates, L.M. Johnson, M.A. Gouker, Advanced fabrication processes for superconducting very large-scale integrated circuits. IEEE Trans. Appl. Supercond. 26(3), 1–10 (2016)

    Article  Google Scholar 

  20. G. Krylov, E.G. Friedman, Design methodology for distributed large-scale ERSFQ bias networks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(11), 2438–2447 (2020)

    Google Scholar 

  21. G. Krylov, E.G. Friedman, Asynchronous dynamic single flux quantum majority gates. IEEE Trans. Appl. Supercond. 30(5), 1–7 (2020). Art no. 1300907

    Google Scholar 

  22. T. Jabbari, E.G. Friedman, Inductive and capacitive coupling noise in superconductive VLSI circuits. IEEE Trans. Appl. Supercond. 33(9), 3800707 (2023)

    Google Scholar 

  23. H. Kumar, T. Jabbari, G. Krylov, K. Basu, E.G. Friedman, R. Karri, Toward increasing the difficulty of reverse engineering of RSFQ circuits. IEEE Trans. Appl. Supercond. 30(3), 1–13 (2020)

    Article  Google Scholar 

  24. Y. Mustafa, T. Jabbari, S. Köse, Emerging attacks on logic locking in SFQ circuits and related countermeasures. IEEE Trans. Appl. Supercond. 32(3), 1–8 (2022)

    Article  Google Scholar 

  25. G. Krylov, E.G. Friedman, Bias distribution in ERSFQ VLSI circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems (2020), pp. 1–5

    Google Scholar 

  26. G. Krylov, E.G. Friedman, Design for testability of SFQ circuits. IEEE Trans. Appl. Supercond. 27(8), 1–7 (2017)

    Article  Google Scholar 

  27. E. Salman, E.G. Friedman, High Performance Integrated Circuit Design (McGraw-Hill Publishers, New York City, 2012)

    Google Scholar 

  28. G. Krylov, E.G. Friedman, Globally asynchronous, locally synchronous clocking and shared interconnect for large-scale SFQ systems. IEEE Trans. Appl. Supercond. 29(5), 1–5 (2019)

    Google Scholar 

  29. K. Gaj, E.G. Friedman, M.J. Feldman, Timing of multi-gigahertz rapid single flux quantum digital circuits. J. VLSI Sig. Process. Syst. 16(2/3), 247–276 (1997)

    Article  Google Scholar 

  30. T. Jabbari, R. Bairamkulov, J. Kawa, E. Friedman, Interconnect benchmark circuits for single flux quantum integrated circuits. IEEE Trans. Appl. Supercond. (2023). Under review

    Google Scholar 

  31. L. Amarú, P. Gaillardon, G. De Micheli, Majority-inverter graph: a new paradigm for logic optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35(5), 806–819 (2016)

    Article  Google Scholar 

  32. E. Testa, M. Soeken, L.G. Amarú, G. De Micheli, Logic synthesis for established and emerging computing. Proc. IEEE 107(1), 165–184 (2019)

    Article  Google Scholar 

  33. K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, N. Yoshikawa, Simulation and experimental demonstration of logic circuits using an ultra-low-power adiabatic quantum-flux-parametron. IEEE Trans. Appl. Supercond. 23(3), 1301105 (2013)

    Google Scholar 

  34. A.L. Braun, Large fan-in RQL gates, U.S. Patent, No. 10,171,087, 1 Jan 2019

    Google Scholar 

  35. S.V. Rylov, Clockless dynamic SFQ and gate with high input skew tolerance. IEEE Trans. Appl. Supercond. 29(5), 1–5 (2019)

    Article  Google Scholar 

  36. A. Silver, R. Phillips, R. Sandell, High speed non-latching SQUID binary ripple counter. IEEE Trans. Magn. 21(2), 204–207 (1985)

    Article  Google Scholar 

  37. S.B. Kaplan, A.F. Kirichenko, O.A. Mukhanov, S. Sarwana, A prescaler circuit for a superconductive time-to-digital converter. IEEE Trans. Appl. Supercond. 11(1), 513–516 (2001)

    Article  Google Scholar 

  38. L. Amarú, P. Gaillardon, A. Chattopadhyay, G. De Micheli, A sound and complete axiomatization of majority-n logic. IEEE Trans. Comput. 65(9), 2889–2895 (2016)

    Article  MathSciNet  Google Scholar 

  39. S.R. Whiteley, WRspice Reference Manual [Online]. Available: http://www.wrcad.com/manual/wrsmanual.pdf

  40. C.J. Fourie, O. Wetzstein, T. Ortlepp, J. Kunert, Three-dimensional multi-terminal superconductive integrated circuit inductance extraction. Supercond. Sci. Technol. 24(12), 125015 (2011)

    Google Scholar 

  41. L. Amarú, P. Gaillardon, S. Mitra, G. De Micheli, New logic synthesis as nanotechnology enabler. Proc. IEEE 103(11), 2168–2195 (2015)

    Article  Google Scholar 

  42. P. Bunyk, K. Likharev, D. Zinoviev, RSFQ technology: physics and devices. Int. J. High Speed Electron. Syst. 11(1), 257–305 (2001)

    Article  Google Scholar 

  43. D. Amparo, M. Eren Çelik, S. Nath, J.P. Cerqueira, A. Inamdar, Timing characterization for RSFQ cell library. IEEE Trans. Appl. Supercond. 29(5), 1–9 (2019)

    Article  Google Scholar 

  44. X. Liu, M.C. Papaefthymiou, E.G. Friedman, Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21(2), 184–203 (2002)

    Article  Google Scholar 

  45. R. Cai, O. Chen, A. Ren, N. Liu, C. Ding, N. Yoshikawa, Y. Wang, A majority logic synthesis framework for adiabatic quantum-flux-parametron superconducting circuits, in Proceedings of the ACM Great Lakes Symposium on VLSI (2019), pp. 189–194

    Google Scholar 

  46. K. Jackman, C.J. Fourie, Flux trapping analysis in superconducting circuits. IEEE Trans. Appl. Supercond. 27(4), 1–5 (2017)

    Article  Google Scholar 

  47. V.K. Semenov, M.M. Khapaev, How moats protect superconductor films from flux trapping. IEEE Trans. Appl. Supercond. 26(3), 1–10 (2016)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Walther Meissner Institute, Bavarian Academy of Sciences and Humanities, Garching, Germany

    Gleb Krylov

  2. University of Rochester, Rochester, NY, USA

    Tahereh Jabbari

  3. University of Rochester, Rochester, NY, USA

    Eby G. Friedman

Authors
  1. Gleb Krylov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Tahereh Jabbari
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Eby G. Friedman
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Gleb Krylov , Tahereh Jabbari or Eby G. Friedman .

Rights and permissions

Reprints and permissions

Copyright information

© 2024 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Krylov, G., Jabbari, T., Friedman, E.G. (2024). Dynamic Single Flux Quantum Majority Gates. In: Single Flux Quantum Integrated Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-031-47475-0_7

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-47475-0_7

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-47474-3

  • Online ISBN: 978-3-031-47475-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation