Benchmark Circuits for Single Flux Quantum Integrated Systems

Abstract

Superconductive single flux quantum (SFQ) technology is one of the most promising beyond CMOS technologies for large-scale, high-performance computing systems. The operating frequency of SFQ circuits may exceed hundreds of gigahertz while dissipating several orders of magnitude lower power, including the refrigeration. Recent advances in SFQ manufacturing technology have enabled significantly higher levels of integration and system complexity. Further advancements in SFQ systems integration require improved design methodologies and flows. The lack of SFQ specific benchmark systems complicates the development and evaluation of these SFQ design flows. This limitation is particularly relevant to the development of physical design tools since existing CMOS benchmark systems are not easily adapted to support SFQ technology. In this chapter, a suite of SFQ specific interconnect routing benchmark systems is presented. The benchmark circuits support the evaluation of data signal, clock signal, and bias current routing algorithms. Due to the gate-level pipelining inherent to SFQ logic, path balancing using D flip flops is required to ensure consistent logic depth and correct operation. Popular CMOS benchmark circuits are converted into SFQ technology, producing SFQ circuits with over 100,000 logic gates. Based on Synopsys EDA tools, the layout of these systems is generated for the MIT LL SFQ5ee technology. Rows of logic cells and passive transmission lines are also included within the layout to manage the interconnect length and delay. The benchmark circuits are openly available to evaluate and enhance state-of-the-art and next-generation physical design of VLSI complexity SFQ systems.

Appendices

Appendix A

1.1 SFQ Interconnect

In SFQ systems, routing methods include passive transmission lines (PTLs) and Josephson transmission lines (JTLs) behaving as interconnects. JTL and PTL interconnects are described, respectively, in subsections A1 and A2.

1.1.1 A1) Josephson Transmission Lines

A JTL is typically composed of uniformly sized Josephson junctions with a uniform inductance L between junctions, as shown in Fig. 30.2a. The number of JTLs depends upon the distance between the SFQ cells. The dimensions of one JTL stage with two JJs are 40 µm $\times$ 20 µm (in the MIT LL 10 kA/cm² technology). For example, for a distance of 500 µm between SFQ cells, 25 JTLs are required. The delay of one JTL stage is about 5 ps. The delay of the JTL interconnects increases linearly with the number of JTL stages [39]. The JTL interconnect is located within the active gate layers. JTL-based SFQ interconnect consumes significant area, power, and delay when connecting distant SFQ circuits, as shown in Fig. 30.9. The power and area overhead of JTL interconnect are a significant challenge for VLSI complexity SFQ circuits.

Fig. 30.9

A comparison between JTL vs. PTL. The JTL has a linewidth of 350 nm (dotted line) and 1 $\upmu$m (dash line). The PTL includes two JJs in the receiver (straight line) and one JJ in the receiver (dash-dotted line)

1.1.2 A2) Passive Transmission Lines

In large-scale SFQ circuits, PTL interconnects connect distant SFQ cells. PTLs decrease the delay of long connections while amenable to automated routing and CTS layout algorithms. A reliable topology for a PTL in the MIT LL 10 kA/cm² technology consists of a superconductive stripline in the routing layers and the driver and receiver within the active gate layers (see Fig. 30.2b) [39]. The length of the line within the routing layer depends upon the distance between the two gates. For long interconnect, the delay and area of a PTL are significantly less than the delay of the JTL interconnect, as shown in Fig. 30.9. Two bias currents are required for the driver and receiver circuits. However, congestion in the routing layers, assuming space within the cell layers is available, can make a JTL the preferable choice for certain interconnect. With the large number of bias currents and JJs in JTL interconnects, however, significant area and energy requirements are introduced into the bias network.

Appendix B

1.1 Superconductive Layout

The layout structure of the MIT LL SFQ5ee process [111] with eight Nb layers is shown in Fig. 30.10. The JJs within an SFQ circuit are placed within the active gate layers, M5 and M6, as shown in Fig. 30.10. The routing lines and inductors are asymmetric striplines, where two signal layers are sandwiched between two ground planes. The ground planes act as nearby return paths for the magnetic currents. The stripline is separated from the lower and upper ground planes by a dielectric layer. For each routing line, no ground plane exists between signal layers. The distance to the ground planes and the thickness of the dielectric layers are therefore different. The inductors and routing striplines are placed, respectively, in the M5 and M6 layers and M2 and M3 layers. Metal resources are severely limited in this modern superconductive technology, as shown in this figure. The width of the PTL striplines is 5.2 µm in the MIT LL SFQ5ee process. Design constraints on the PTLs are discussed in Appendix B1. The structure of the bias lines is described in Appendix B2. Placement constraints are described in Sect. 30.3.2.

Fig. 30.10

Physical topology of superconductive circuits in the MIT LL SFQ5ee process [111, 224]

1.1.1 $(1)$ Grids and Circuit Placement

The connections between the different layers are shown in Fig. 30.3. The JJs in the M5 layer are connected with vias to the inductors in M6, also shown in Fig. 30.3. The bias distribution network is connected to the active layers with vias—M0 to M5 and M6 layers. These vias are connected to JJs with resistors in RSFQ systems and with inductors in efficient single flux quantum (ESFQ) systems.

The two primary bias lines are placed in the M0 layer every 20 $\upmu$m in the horizontal direction, as shown in Fig. 30.3. In addition, a vertical bias line can be placed every 20 $\upmu$m in the M2 layer. These bias lines restrict the vertical PTLs to the M2 layer. The horizontal and vertical PTL interconnects are routed, respectively, within the M3 and M2 layers, every 20 $\upmu$m. The PTL striplines exhibit a low impedance of 8 $\Omega$ with a linewidth of 5.2 $\upmu$m.

The ground layers are stitched within the MIT LL SFQ5ee process to reduce noise coupling of the PTL lines to the different layers [61, 63, 87, 137, 147]. The stitching vias are placed along the PTL with a 0.5 µm space from M7 to M1, as shown in Fig. 30.3. The dimensions of these vias are 2.5 µm by 1.2 µm [576]. The stitching vias along the interconnect and related via constraints need to be considered in the layout of the SFQ benchmark circuits to enhance the robustness of the automatically routed interconnects.

1.1.2 $(2)$ Bias Lines

A JJ loses superconductivity when the bias current exceeds the critical current $I_C$, making $I_C$ a primary parameter of a Josephson junction [25]. The critical current of a JJ depends upon the physical area of the JJs. To maintain proper operation, the JJs within the SFQ circuits are typically biased to 0.7 $\times$ $I_C$ [25]. The large number of JJs and bias currents in JTL and PTL interconnects emphasizes the importance of the distribution network for the bias currents within a complex SFQ system [131].

The bias distribution network within an SFQ system supplies the precise bias current to each JJ. Unlike CMOS power distribution networks, an SFQ bias distribution network is lossless until the load is reached. The bias current is distributed by inductive current division within SFQ circuits [131]. In these circuits, the bias lines and interconnects are placed within the different layers, providing multiple independent paths to feed the different devices. The multiple bias lines enhance the flexibility of the layout topology and bias schemes.

The bias lines within the M0 layer are separated from the upper ground plane, the M1 layer, by a dielectric layer. The width of the bias lines in the MIT LL SFQ5ee process is 1.8 µm [224]. The bias lines carrying high currents can also affect the operation of the PTLs. The design of the bias distribution and signal routing structures requires careful focus to support complex SFQ systems [131].