Interconnect Routing for Large-Scale SFQ Circuits

Abstract

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing an issue of growing importance. In this chapter, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Trade-offs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A trade-off between the PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of $\pm 29\%$ for the bias current of the receiver operating at 20 GHz in a 10 kA/cm${ }^2$ technology for a 1 mm transmission line is achieved. Summarizing, guidelines and design trade-offs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.