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Partitioning RSFQ Circuits for Current Recycling

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Single Flux Quantum Integrated Circuit Design

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Abstract

RSFQ circuits require a DC bias current to operate properly. The bias current in conventional RSFQ circuits is supplied to each gate, resulting in large current requirements in VLSI complexity SFQ systems, on the order of tens to hundreds of amperes. These high currents are difficult to supply and distribute. Large currents require significant metal and input pin resources. In addition, large currents can inductively couple to sensitive superconductive inductors, degrading circuit operation and producing errors. Current recycling is a well-known technique to reduce these bias currents. RSFQ circuits with similar bias current requirements can be serially biased and placed on separate ground planes. The inputs and outputs of these circuits are galvanically decoupled and require drivers and receivers between connections. In this chapter, a methodology for automated partitioning of complex RSFQ circuits into blocks with similar bias currents is described, where the number of connections among the blocks is minimized. These blocks are biased in series, reducing the total bias current by the number of partitions. The partitioning methodology is intended for use within an automated EDA flow to enable current recycling for arbitrary (nonuniform, irregular) VLSI complexity RSFQ circuits, drastically reducing the overall bias current and input requirements.

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References

  1. O.A. Mukhanov, Energy-efficient single flux quantum technology. IEEE Trans. Appl. Supercond. 21(3), 760–769 (2011)

    Article  Google Scholar 

  2. T. Jabbari, G. Krylov, S. Whiteley, E. Mlinar, J Kawa, E.G. Friedman, Interconnect routing for large scale RSFQ circuits. IEEE Trans. Appl. Supercond. 29(5), 1102805 (2019)

    Google Scholar 

  3. T. Jabbari, E.G. Friedman, Global interconnects in VLSI complexity single flux quantum systems, in Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop (2020), pp. 1–7

    Google Scholar 

  4. T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Repeater insertion in SFQ interconnect. IEEE Trans. Appl. Supercond. 30(8), 5400508 (2020)

    Google Scholar 

  5. T. Jabbari, E.G. Friedman, Transmission lines in VLSI complexity single flux quantum systems, in Proceedings of the PhotonIcs and Electromagnetics Research Symposium (2023), pp. 1749–1759

    Google Scholar 

  6. R. Bairamkulov, T. Jabbari, E.G. Friedman, QuCTS – single flux quantum clock tree synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), 3346–3358 (2022)

    Article  Google Scholar 

  7. T. Jabbari, J. Kawa, E.G. Friedman, H-tree clock synthesis in RSFQ circuits, in Proceedings of the IEEE Baltic Electronics Conference (2020), pp. 1–5

    Google Scholar 

  8. T. Jabbari, G. Krylov, J Kawa, E.G. Friedman, Splitter trees in single flux quantum circuits. IEEE Trans. Appl. Supercond. 31(5), 1302606 (2021)

    Google Scholar 

  9. T. Jabbari, E.G. Friedman, Flux mitigation in wide superconductive striplines. IEEE Trans. Appl. Supercond. 32(3), 1–6 (2022)

    Article  Google Scholar 

  10. T. Jabbari, E.G. Friedman, Stripline topology for flux mitigation. IEEE Trans. Appl. Supercond. 335, 1–4 (2023)

    Google Scholar 

  11. T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Resonance effects in single flux quantum interconnect, in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (2020), pp. 1–5

    Google Scholar 

  12. T. Jabbari, E.G. Friedman, Surface inductance of superconductive striplines. IEEE Trans. Circuits Syst. II Express Briefs 69(6), 2952–2956 (2022)

    Google Scholar 

  13. S.K. Tolpygo, Superconductor digital electronics: scalability and energy efficiency issues. Low Temp. Phys. 42(5), 361–379 (2016)

    Article  Google Scholar 

  14. G. Krylov, E.G. Friedman, Partitioning RSFQ circuits for current recycling. IEEE Trans. Appl. Supercond. 31(5), 1–6 (2021)

    Article  Google Scholar 

  15. G. Krylov, E.G. Friedman, Design methodology for distributed large-scale ERSFQ bias networks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(11), 2438–2447 (2020)

    Google Scholar 

  16. G. Krylov, E.G. Friedman, Asynchronous dynamic single flux quantum majority gates. IEEE Trans. Appl. Supercond. 30(5), 1–7 (2020). Art no. 1300907

    Google Scholar 

  17. T. Jabbari, E.G. Friedman, Inductive and capacitive coupling noise in superconductive VLSI circuits. IEEE Trans. Appl. Supercond. 33(9), 3800707 (2023)

    Google Scholar 

  18. H. Kumar, T. Jabbari, G. Krylov, K. Basu, E.G. Friedman, R. Karri, Toward increasing the difficulty of reverse engineering of RSFQ circuits. IEEE Trans. Appl. Supercond. 30(3), 1–13 (2020)

    Article  Google Scholar 

  19. Y. Mustafa, T. Jabbari, S. Köse, Emerging attacks on logic locking in SFQ circuits and related countermeasures. IEEE Trans. Appl. Supercond. 32(3), 1–8 (2022)

    Article  Google Scholar 

  20. G. Krylov, E.G. Friedman, Bias distribution in ERSFQ VLSI circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems (2020), pp. 1–5

    Google Scholar 

  21. G. Krylov, E.G. Friedman, Bias networks for high complexity energy efficient single flux quantum circuits, in Proceedings of the Government Microcircuit Applications & Critical Technology Conference (2020)

    Google Scholar 

  22. G. Krylov, E.G. Friedman, Design for testability of SFQ circuits. IEEE Trans. Appl. Supercond. 27(8), 1–7 (2017)

    Article  Google Scholar 

  23. V.K. Semenov, Y.A. Polyakov, S.K. Tolpygo, Very large scale integration of Josephson-junction-based superconductor random access memories. IEEE Trans. Appl. Supercond. 29(5), 1–9 (2019)

    Google Scholar 

  24. G. Krylov, E.G. Friedman, Globally asynchronous, locally synchronous clocking and shared interconnect for large-scale SFQ systems. IEEE Trans. Appl. Supercond. 29(5), 1–5 (2019)

    Google Scholar 

  25. N.K. Katam, O. Mukhanov, M. Pedram, Simulation analysis and energy-saving techniques for ERSFQ circuits. IEEE Trans. Appl. Supercond. 29(5), 1–7 (2019)

    Article  Google Scholar 

  26. T. Jabbari, R. Bairamkulov, J. Kawa, E. Friedman, Interconnect benchmark circuits for single flux quantum integrated circuits. IEEE Trans. Appl. Supercond. (2023). Under review

    Google Scholar 

  27. A.B. Kahng, J. Lienig, I.L. Markov, J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure (Springer Netherlands, Dordrecht, 2011)

    Book  Google Scholar 

  28. C.M. Fiduccia, R.M. Mattheyses, A linear-time heuristic for improving network partitions, in Proceedings of the ACM/IEEE Design Automation Conference (1982), pp. 175–181

    Google Scholar 

  29. V.K. Semenov, Y. Polyakov, Current recycling: new results. IEEE Trans. Appl. Supercond. 29(5), 1–4 (2019)

    Google Scholar 

  30. J.H. Kang, S.B. Kaplan, Current recycling and SFQ signal transfer in large scale RSFQ circuits. IEEE Trans. Appl. Supercond. 13(2), 547–550 (2003)

    Article  Google Scholar 

  31. M.W. Johnson, Q.P. Herr, D.J. Durand, L.A. Abelson, Differential SFQ transmission using either inductive or capacitive coupling. IEEE Trans. Appl. Supercond. 13(2), 507–510 (2003)

    Article  Google Scholar 

  32. K. Sano, T. Shimoda, Y. Abe, Y. Yamanashi, N. Yoshikawa, N. Zen, M. Ohkubo, Reduction of the supply current of single-flux-quantum time-to-digital converters by current recycling techniques. IEEE Trans. Appl. Supercond. 27(4), 1–5 (2017)

    Article  Google Scholar 

  33. V.K. Semenov, M.A. Voronova, DC voltage multipliers: a novel application of synchronization in Josephson junction arrays. IEEE Trans. Magn. 25(2), 1432–1435 (1989)

    Article  Google Scholar 

  34. T.V. Filippov, A. Sahu, S. Sarwana, D. Gupta, V.K. Semenov, Serially biased components for digital-RF receiver. IEEE Trans. Appl. Supercond. 19(3), 580–584 (2009)

    Article  Google Scholar 

  35. G. Krylov, E.G. Friedman, Partitioning of RSFQ circuits for current recycling, in Proceedings of the IEEE Applied Superconductivity Conference (2020)

    Google Scholar 

  36. N.K. Katam, B. Zhang, M. Pedram, Ground plane partitioning for current recycling of superconducting circuits, in Proceedings of the ACM/IEEE Design, Automation & Test in Europe Conference (2020), pp. 478–483

    Google Scholar 

  37. D.A. Papa, I.L. Markov, Hypergraph partitioning and clustering, in Handbook of Approximation Algorithms and Metaheuristics (Chapman & Hall/CRC, Boca Raton, 2007)

    Google Scholar 

  38. T. Manikas, G.R. Kane, Partitioning effects on estimated wire length for mixed macro and standard cell placement, in Proceedings of the ACM/IEEE International Workshop on Logic and Synthesis (2002)

    Google Scholar 

  39. C.J. Alpert, A.E. Caldwell, A.B. Kahng, I.L. Markov, Hypergraph partitioning with fixed vertices. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 19(2), 267–272 (2000)

    Article  Google Scholar 

  40. C.J. Alpert, T. Chan, D. Huang, I.L. Markov, K. Yan, Quadratic placement revisited, in Proceedings of the ACM/IEEE Design Automation Conference (1997), pp. 752–757

    Google Scholar 

  41. R. Tsay, E.S. Kuh, C. Hsu, PROUD: a sea-of-gates placement algorithm. IEEE Des. Test Comput. 5(6), 44–56 (1988).

    Article  Google Scholar 

  42. B.W. Kernighan, S. Lin, An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 49(2), 291–307 (1970)

    Article  Google Scholar 

  43. F. Brglez, D. Bryan, K. Kozminski, Combinational profiles of sequential benchmark circuits. Proc. IEEE Int. Sympos. Circuits Syst. 3, 1929–1934 (1989)

    Article  Google Scholar 

  44. F.M. Johannes, Partitioning of VLSI circuits and systems, in Proceedings of the ACM/IEEE Design Automation Conference (1996), pp. 83–87

    Google Scholar 

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Authors and Affiliations

  1. Bavarian Academy of Sciences and Humanities, Garching, Germany

    Gleb Krylov

  2. University of Rochester, Rochester, USA

    Tahereh Jabbari

  3. University of Rochester, Rochester, USA

    Eby G. Friedman

Authors
  1. Gleb Krylov
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  2. Tahereh Jabbari
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  3. Eby G. Friedman
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Correspondence to Gleb Krylov , Tahereh Jabbari or Eby G. Friedman .

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Krylov, G., Jabbari, T., Friedman, E.G. (2024). Partitioning RSFQ Circuits for Current Recycling. In: Single Flux Quantum Integrated Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-031-47475-0_16

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  • DOI: https://doi.org/10.1007/978-3-031-47475-0_16

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  • Publisher Name: Springer, Cham

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  • Online ISBN: 978-3-031-47475-0

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