Abstract
Rapid single-flux quantum (RSFQ) technology promises high-performance, energy-efficient supercomputers to achieve exascale computing. An important challenge in VLSI complexity RSFQ circuits is ultra-high-speed clocking and synchronization. A methodology to support the automated design of clock distribution networks for SFQ circuits is the focus of this chapter. Global clock synthesis of SFQ circuits is applied to produce a near-zero skew clock network. An algorithm is presented that produces an SFQ H-tree network with asymmetric leaves to propagate the clock signal to all SFQ gates. A Python-based system with location information for the interconnects, splitters, and leaves is described. The algorithm determines the physical locations and connections within the SFQ clock network and is applicable to automated routing and clock tree synthesis.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
K.K. Likharev, V.K. Semenov, RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. IEEE Trans. Appl. Supercond. 1(1), 3–28 (1991)
D.S. Holmes, A.L. Ripple, M.A. Manheimer, Energy-efficient superconducting computing—power budgets and requirements. IEEE Trans. Appl. Supercond. 23(3), 1701610 (2013)
T. Jabbari, G. Krylov, S. Whiteley, E. Mlinar, J Kawa, E.G. Friedman, Interconnect routing for large scale RSFQ circuits. IEEE Trans. Appl. Supercond. 29(5), 1102805 (2019)
T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Global signaling for large scale RSFQ circuits, in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (2019), pp. 1–6
T. Jabbari, E.G. Friedman, Global interconnects in VLSI complexity single flux quantum systems, in Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop (2020), pp. 1–7
T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Repeater insertion in SFQ interconnect. IEEE Trans. Appl. Supercond. 30(8), 5400508 (2020)
T. Jabbari, E.G. Friedman, Transmission lines in VLSI complexity single flux quantum systems, in Proceedings of the PhotonIcs and Electromagnetics Research Symposium (2023), pp. 1749–1759
R. Bairamkulov, T. Jabbari, E.G. Friedman, QuCTS – single flux quantum clock tree synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), 3346–3358 (2022)
T. Jabbari, J. Kawa, E.G. Friedman, H-tree clock synthesis in RSFQ circuits, in Proceedings of the IEEE Baltic Electronics Conference (2020), pp. 1–5
T. Jabbari, G. Krylov, J Kawa, E.G. Friedman, Splitter trees in single flux quantum circuits. IEEE Trans. Appl. Supercond. 31(5), 1302606 (2021)
T. Jabbari, E.G. Friedman, Flux mitigation in wide superconductive striplines. IEEE Trans. Appl. Supercond. 32(3), 1–6 (2022)
T. Jabbari, E.G. Friedman, Stripline topology for flux mitigation. IEEE Trans. Appl. Supercond. 335, 1–4 (2023)
T. Jabbari, G. Krylov, S. Whiteley, J. Kawa, E.G. Friedman, Resonance effects in single flux quantum interconnect, in Proceedings of the Government Microcircuit Applications and Critical Technology Conference (2020), pp. 1–5
T. Jabbari, E.G. Friedman, Surface inductance of superconductive striplines. IEEE Trans. Circuits Syst. II Express Briefs 69(6), 2952–2956 (2022)
Y. Ando, R. Sato, M. Tanaka, K. Takagi, N. Takagi, A. Fujimaki, Design and demonstration of an 8-bit bit-serial RSFQ microprocessor: CORE e4. IEEE Trans. Appl. Supercond. 26(5), 1301205 (2016)
K. Gaj, E.G. Friedman, M.J. Feldman, Timing of multi-gigahertz rapid single flux quantum digital circuits. J. VLSI Sig. Process. Syst. 16(2/3), 247–276 (1997)
S.N. Shahsavani, T. Lin, A. Shafaei, C.J. Fourie, M. Pedram, An integrated row-based cell placement and interconnect synthesis tool for large SFQ logic circuits. IEEE Trans. Appl. Supercond. 27(4), 1–8 (2017)
RSFQ @ SUNY Stony Brook, June 2019 [Online]. Available: http://www.physics.sunysb.edu/Physics/RSFQ/index.html
E.G. Friedman, Clock distribution design in VLSI circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems (1993), pp. 1475–1478
E.G. Friedman, Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE 89(5), 665–692 (2001)
P. Bunyk, K. Likharev, D. Zinoviev, RSFQ technology: physics and devices. Int. J. High Speed Electron. Syst. 11(1), 257–305 (2001)
R.N. Tadros, P.A. Beerel, A robust and self-adaptive clocking technique for SFQ circuits. IEEE Trans. Appl. Supercond. 28(7), 1301211 (2018)
T. Van Duzer, L. Zheng, X. Meng, C. Loyo, S.R. Whiteley, L. Yu, N. Newman, J.M. Rowell, N. Yoshikawa, Engineering issues in high-frequency RSFQ circuits. Phys. C Supercond. 372(1), 1–6 (2002)
J.L. Neves, E.G. Friedman, Topological design of clock distribution networks based on non-zero clock skew specifications, in Proceedings of the IEEE Midwest Symposium on Circuits and Systems (1993), pp. 468–471
J. Rosenfeld, E.G. Friedman, Design methodology for global resonant H-tree clock distribution networks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(2), 135–148 (2007)
W.R. Migatz, P.M. Campbell, D.J. Hathaway, D.S. Kung, R. Puri, L.H. Trevillyan, Clock tree distribution generation by determining allowed placement regions for clocked elements, No. 7,225,421 (2007)
Niobium Process - Hypres, Inc., June (2019) [Online]. Available: https://www.hypres.com/foundry/niobium-process
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
Copyright information
© 2024 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this chapter
Cite this chapter
Krylov, G., Jabbari, T., Friedman, E.G. (2024). H-Tree Clock Synthesis in SFQ Circuits. In: Single Flux Quantum Integrated Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-031-47475-0_13
Download citation
DOI: https://doi.org/10.1007/978-3-031-47475-0_13
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-47474-3
Online ISBN: 978-3-031-47475-0
eBook Packages: EngineeringEngineering (R0)