Abstract
System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units are defective. CLR even enables selling lower end products if more cores have failed than needed by the most demanding applications. In the current contribution the mechanisms built for CLR are used to increase throughput while complying with the Thermal Design Power (TDP) constraints. We propose NTHPC, that utilizes the designed redundancy support to improve system performance without violating thermal limits. This is done by operating the logic at a voltage close to the threshold voltage of the transistors. Our study using an Intel Xeon multiprocessor shows that Near Threshold Computing (NTC) with CLR mechanisms for thermal controls enabled up to 10.8% average throughput improvement in comparison to plain power gating.
This work was supported by Academy of Finland 6G flagship programme (Grant Number 318927) and by Marie Curie Individual Fellowship (MSCA-IF), EU (Grant Number 898296).
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References
https://patents.google.com/patent/US8074110. Accessed 30 Dec 2022
Bienia, C., et al.: The PARSEC benchmark suite: characterization and architectural implications. In: PACT (2008)
Binkert, N., et al.: The Gem5 simulator. SIGARCH Comput. Archit. News 39, 1–7 (2011)
Cai, E., Marculescu, D.: Temperature effect inversion-aware power-performance optimization for FinFET-based multicore systems. IEEE TCAD 36, 1897–1910 (2017)
Chakraborty, S., et al.: STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. In: CF (2022)
Dreslinski, R.G., et al.: Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. In: Proceedings of the IEEE (2010)
Guler, A., Jha, N.K.: McPAT-monolithic: an area/power/timing architecture modeling framework for 3-D hybrid monolithic multicore systems. IEEE TVLSI 28(10), 2146–2156 (2020)
Iverson, D., et al.: Redundant core testing on the cell BE microprocessor. In: International Test Conference. IEEE (2010)
Lee, W., et al.: TEI-power: temperature effect inversion-aware dynamic thermal management. ACM TODAES 22(3), 1–25 (2017)
Meyer, B.H., et al.: Cost-effective lifetime and yield optimization for NoC-based MPSoCs. ACM TODAES 19(2), 1–33 (2014)
Mozafari, S.H., Meyer, B.H.: Characterizing the effectiveness of hot sparing on cost and performance-per-watt in application specific SIMT. Integration 69, 198–209 (2019)
Mozafari, S.H., Meyer, B.H.: Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors. Des. Autom. Embedded Syst. 24, 249–266 (2020)
Naffziger, S., et al.: 2.2 AMD chiplet architecture for high-performance server and desktop products. In: ISSCC (2020)
Safarpour, M., Silvén, O.: LoFFT: low-voltage FFT using lightweight fault detection for energy efficiency. IEEE Embedded Syst. Lett. (2022)
Vera, X., et al.: Enhancing reliability of a many-core processor (2011), US Patent 8,074,110
Zhang, L., et al.: Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology. In: DATE (2008)
Zhang, R., et al.: HotSpot 6.0: Validation, acceleration and extension. In: University of Virginia, Technical report, CS-2015-04 (2015)
Zu, Y., et al.: T i-states: processor power management in the temperature inversion region. In: MICRO (2016)
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Chakraborty, S., Safarpour, M., Silvén, O. (2023). NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. In: Silvano, C., Pilato, C., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023. Lecture Notes in Computer Science, vol 14385. Springer, Cham. https://doi.org/10.1007/978-3-031-46077-7_3
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