Abstract
The emergence of a new, open, and free instruction set architecture, RISC-V, has heralded a new era in microprocessor architectures. Starting with low-power, low-performance prototypes, the RISC-V community has a good chance of moving towards fully functional high-end microprocessors suitable for high-performance computing. Achieving progress in this direction requires comprehensive development of the software environment, namely operating systems, compilers, mathematical libraries, and approaches to performance analysis and optimization. In this paper, we analyze the performance of two available RISC-V devices when executing three memory-bound applications: a widely used STREAM benchmark, an in-place dense matrix transposition algorithm, and a Gaussian Blur algorithm. We show that, compared to x86 and ARM CPUs, RISC-V devices are still expected to be inferior in terms of computation time but are very good in resource utilization. We also demonstrate that well-developed memory optimization techniques for x86 CPUs improve the performance on RISC-V CPUs. Overall, the paper shows the potential of RISC-V as an alternative architecture for high-performance computing.
Keywords
- High-Performance Computing
- RISC-V
- ISA
- C++
- Performance Analysis and Optimization
- Memory-Bound Applications
This is a preview of subscription content, access via your institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
In the case of using processors with RISC-V architecture, the OpenCV computation time was measured on a Linux image that supports vector instructions.
References
Asanović, K., Patterson, D.A.: Instruction sets should be free: the case for RISC-V. EECS Department. University of California, Berkeley. UCB/EECS-2014–146 (2014)
Waterman, A., Asanović, K.: The RISC-V instruction set manual, volume I: user-level ISA, document version 20190608-base-ratified. In: RISC-V Foundation (2019)
Furber, S.B.: VLSI RISC Architecture and Organization, 1st edn. CRC Press (1989)
Asanović, K.: Advancing HPC with RISC-V. In: Invited Talk at Supercomputing Conference (2022)
McCalpin, J.: Memory bandwidth and machine balance in current high performance computers. IEEE Comput. TCCA Newsl., 19–24 (1995)
History – RISC-V International. https://riscv.org/about/history/. Accessed 09 May 2023
Chen, T., Patterson, D.A.: RISC-V genealogy. EECS Department, University of California, Berkeley, Technical report UCB/EECS-2016-6 (2016)
Waterman, A., Asanovic, K., Hauser, J.: The RISC-V instruction set manual, Volume II: privileged architecture, document version 20211203 (2021)
Lee, Y., et al.: Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. In: 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1–45. IEEE (2015)
Zimmer, B., et al.: A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. In: 2015 VLSI Circuits, pp. 316–317. IEEE (2015)
Schmidt, C., et al.: Programmable fine-grained power management and system analysis of RISC-V vector processors in 28-nm FD-SOI. IEEE Solid State Circuits Lett. 3, 210–213 (2020)
Wright, J.C., et al.: A dual-core RISC-V vector processor with on-chip fine-grain power management in 28-nm FD-SOI. IEEE Trans. VLSI Syst. 28(12), 2721–2725 (2020)
Celio, C., et al.: BROOM: an open-source out-of-order processor with resilient low-voltage operation in 28-nm CMOS. IEEE Micro 39(2), 52–60 (2019)
Zhao, J., et al.: SonicBOOM: the 3rd generation berkeley out-of-order machine. In: Fourth Workshop on Computer Architecture Research with RISC-V, vol. 5, pp. 1–7 (2020)
RISC-V BOOM. https://boom-core.org/. Accessed 09 May 2023
BOOM: The Berkeley out-of-order RISC-V Processor. https://github.com/riscv-boom. Accessed 09 May 2023
Bartolini, A., et al.: Monte cimone: paving the road for the first generation of RISC-V high-performance computers. In: 2022 IEEE 35th International System-on-Chip Conference (SOCC), pp. 1–6. IEEE (2022)
Europe steps up as RISC-V ships 10bn cores. https://www.eenewseurope.com/en/europe-steps-up-as-risc-v-ships-10bn-cores/. Accessed 09 May 2023
RISC-V Software Ecosystem Status. https://sites.google.com/riscv.org/software-ecosystem-status. Accessed 09 May 2023
Davis, J.D.: RISC-V in Europe: the road to an open source HPC stack. https://www.european-processor-initiative.eu/wp-content/uploads/2022/03/EPI-@-HPC-User-Forum.pdf. Accessed 09 May 2023
First International workshop on RISC-V for HPC. https://riscv.epcc.ed.ac.uk/community/isc23-workshop/. Accessed 09 May 2023
RISC-V ISA – MIPS. https://www.mips.com/products/risc-v/. Accessed 09 May 2023
Framework Partnership Agreement for developing a large-scale European initiative for HPC ecosystem based on RISC-V. https://eurohpc-ju.europa.eu/framework-partnership-agreement-fpa-developing-large-scale-european-initiative-high-performance_en. Accessed 09 May 2023
Chatterjee, S., Sen, S.: Cache-efficient matrix transposition. In: IEEE Proceedings Sixth International Symposium on High-Performance Computer Architecture, HPCA-6 (Cat. No. PR00550), pp. 195–205 (2000)
Moradifar, M., Shahbahrami, A.: Performance improvement of Gaussian filter using SIMD technology. In: International Conference on Machine Vision and Image Processing, pp. 1–6 (2020)
Acknowledgements
The study is supported by the Lobachevsky University academic leadership program “Priority-2030”. Experiments were performed on the Lobachevsky supercomputer.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Volokitin, V., Kozinov, E., Kustikova, V., Liniov, A., Meyerov, I. (2023). Case Study for Running Memory-Bound Kernels on RISC-V CPUs. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2023. Lecture Notes in Computer Science, vol 14098. Springer, Cham. https://doi.org/10.1007/978-3-031-41673-6_5
Download citation
DOI: https://doi.org/10.1007/978-3-031-41673-6_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-41672-9
Online ISBN: 978-3-031-41673-6
eBook Packages: Computer ScienceComputer Science (R0)