Abstract
Domain-specific neural network accelerators have seen growing interest in recent years due to their improved energy-efficiency and inference performance compared to CPUs and GPUs. In this chapter, we propose a novel co-designed neural network accelerator called CrossLight that leverages silicon photonics. CrossLight includes device-level engineering for resilience to process variations and thermal crosstalk, circuit-level tuning enhancements for inference latency reduction, and architecture-level optimization to enable higher resolution, better energy-efficiency, and improved throughput. On average, CrossLight offers 9.5× lower energy per bit and 15.9× higher performance per watt at 16-bit resolution than state-of-the-art photonic deep learning accelerators.
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References
Jouppi, N.P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., Boyle, R., Cantin, P., Chao, C., Clark, C., Coriell, J., Daley, M., Dau, M., Dean, J., Gelb, B., Ghaemmaghami, T.V., Gottipati, R., Gulland, W., Hagmann, R., Ho, C.R., Hogberg, D., Hu, J., Hundt, R., Hurt, D., Ibarz, J., Jaffey, A., Jaworski, A., Kaplan, A., Khaitan, H., Koch, A., Kumar, N., Lacy, S., Laudon, J., Law, J., Le, D., Leary, C., Liu, Z., Lucke, K., Lundin, A., MacKean, G., Maggiore, A., Mahony, M., Miller, K., Nagarajan, R., Narayanaswami, R., Ni, R., Nix, K., Norrie, T., Omernick, M., Penukonda, N., Phelps, A., Ross, J., Ross, M., Salek, A., Samadiani, E., Severn, C., Sizikov, G., Snelham, M., Souter, J., Steinberg, D., Swing, A., Tan, M., Thorson, G., Tian, B., Toma, H., Tuttle, E., Vasudevan, V., Walter, R., Wang, W., Wilcox, E., Yoon, D.H.: In-datacenter performance analysis of a tensor processing unit. In: ISCA 2017
Intel Movidius VPU.: 2020, [Online]: https://www.intel.com/content/www/us/en/products/processors/movidius-vpu/movidius-myriad-x.html
Waldrop, M.M.: The chips are down for Moore’s law. Nat. News. 530(7589) (2016)
Pasricha, S., Dutt, N.: On-Chip Communication Architectures. Morgan Kauffman, ISBN 978-0-12-373892-9 (Apr 2008)
Ziabari, A.K.K., Abella’n, J.L., Ubal, R., Chen, C., Joshi, A., Kaeli, D.: Leveraging silicon-photonic noc for designing scalable GPUs. In: ACM ICS (2015)
Bahirat, S., Pasricha, S.: METEOR: hybrid photonic ring-mesh network-on-chip for multicore architectures. ACM Trans. Embedd. Comput. Syst. 13(3), 1–33 (2014)
Bahirat, S., Pasricha, S.: HELIX: design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures. IEEE international symposium on quality electronic design (ISQED), 2014.
Bahirat, S., Pasricha, S.: 3D HELIX: design and synthesis of hybrid nanophotonic application-specific 3D network-on-chip architectures. Workshop on exploiting silicon photonics for energy efficient heterogeneous parallel architectures (SiPhotonics), 2014.
Bahirat, S., Pasricha, S.: A particle Swarm optimization approach for synthesizing application-specific hybrid photonic networks-on-chip. IEEE international symposium on quality electronic design (ISQED), 2012.
Bahirat, S., Pasricha, S.: UC-PHOTON: a novel hybrid photonic network-on-chip for multiple use-case applications. IEEE international symposium on quality electronic design (ISQED), 2010.
Bahirat, S., Pasricha, S.: Exploring hybrid photonic networks-on-chip for emerging chip multiprocessors. IEEE/ACM international conference on hardware/software codesign and system synthesis (CODES+ISSS), 2009.
Chittamuru, S.V.R., Thakkar, I., Pasricha, S., Vatsavai, S.S., Bhat, V.: Exploiting process variations to secure photonic NoC architectures from snooping attacks. IEEE Trans. Comput. Aid. Des. Integrat. Circuits Syst. 40, 850–863 (2021)
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: LIBRA: thermal and process variation aware reliability management in photonic networks-on-chip. IEEE Tran. Multi-Scale Comput. Syst. 4(4), 758–772 (2018)
Chittamuru, S.V.R., Dharnidhar, D., Pasricha, S., Mahapatra, R.: BiGNoC: accelerating Big Data computing with application-specific photonic network-on-chip architectures. IEEE Trans. Parallel. Distrib. Syst. 29(11), 2402–2415 (2018)
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: HYDRA: heterodyne crosstalk mitigation with double microring resonators and data encoding for photonic NoC. IEEE Trans. Very Large Scale Integr. Syst. 26(1), 168–181 (2018)
Chittamuru, S.V.R., Desai, S., Pasricha, S.: SWIFTNoC: a reconfigurable silicon-photonic network with multicast enabled channel sharing for multicore architectures. ACM J. Emerg. Technol. Comput. Syst. 13(4), 1–27 (2017)
Chittamuru, S.V.R., Pasricha, S.: Crosstalk mitigation for high-radix and low-diameter photonic NoC architectures. IEEE Des. Test. 32(3) (2015)
Thakkar, I., Chittamuru, S.V.R., Pasricha, S.: Mitigating the energy impacts of VBTI aging in photonic networks-on-chip architectures with multilevel signaling. IEEE workshop on energy-efficient networks of computers (E2NC), 2018.
Pasricha, S., Chittamuru, S.V.R., Thakkar, I., Bhat, V.: Securing photonic NoC architectures from hardware Trojans. In: IEEE/ACM international symposium on networks-on-chip (NOCS), 2018
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. IEEE/ACM design automation conference (DAC), 2018.
Thakkar, I., Chittamuru, S.V.R., Pasricha, S.: Improving the reliability and energy-efficiency of high-bandwidth photonic NoC architectures with multilevel signaling. IEEE/ACM international symposium on networks-on-chip (NOCS), 2017.
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. ACM system level interconnect prediction workshop (SLIP), 2017.
Dang, D., Chittamuru, S.V.R., Mahapatra, R.N., Pasricha, S.: Islands of heaters: a novel thermal management framework for photonic NoCs. IEEE/ACM Asia & South Pacific design automation conference (ASPDAC), 2017.
Thakkar, I., Chittamuru, S.V.R., Pasricha, S.: A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects. ACM/IEEE system level interconnect prediction workshop (SLIP), 2016.
Thakkar, I., Chittamuru, S.V.R., Pasricha, S.: Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers. IEEE/ACM international symposium on networks-on-chip (NOCS), 2016.
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: PICO: mitigating Heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. IEEE/ACM design automation conference (DAC), 2016.
Chittamuru, S.V.R., Thakkar, I., Pasricha, S.: Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures. IEEE international symposium on quality electronic design (ISQED), 2016.
Chittamuru, S.V.R., Pasricha, S.: SPECTRA: a framework for thermal reliability management in silicon-photonic networks-on-chip. IEEE international conference on VLSI design (VLSI), 2016.
Pasricha, S., Nikdast, M.: A survey of silicon photonics for energy efficient Manycore computing. IEEE Des. Test. 37(4) (2020)
Miller, D.A.: Silicon photonics: meshing optics with applications. Nat. Photonics. 11(7), 403–404 (2017)
Shen, Y., Harris, N.C., Skirlo, S., Prabhu, M., Jones, T.B., Hochberg, M., Sun, X., Zhao, S., Larochelle, H., Englund, D., Soljacic, M.: Deep learning with coherent nanophotonic circuits. Nat. Photonics. 11(7), 441–446 (2017)
Zortman, W.A., Trotter, D.C., Watts, M.R.: Silicon photonics manufacturing. Opt. Express. 18(23) (2010)
Sunny, F., Mirza, A., Nikdast, M., Pasricha, S.: CrossLight: a cross-layer optimized silicon photonic neural network accelerator. ACM/IEEE DAC. (2021)
Sunny, F., Taheri, E., Nikdast, M., Pasricha, S.: A survey on silicon photonics for deep learning. ACM J. Emerg. Technol. Comput. Syst. 17(4), 1–57 (2021)
Tait, A.N., De Lima, T.F., Zhou, E., Wu, A.X., Nahmias, M.A., Shastri, B.J., Prucnal, P.R.: Neuromorphic photonic networks using silicon photonic weight banks. Sci. Rep. 7(1) (2017)
Bangari, V., Marquez, B.A., Miller, H., Tait, A.N., Nahmias, M.A., De Lima, T.F., Peng, H.T., Prucnal, P.R., Shastri, B.J.: Digital electronics and analog photonics for convolutional neural networks (DEAP-CNNs). IEEE JQE. 26(1) (2020)
Liu, W., Liu, W., Ye, Y., Lou, Q., Xie, Y., Jiang, L.: HolyLight: a Nanophotonic accelerator for deep learning in data centers. In: IEEE/ACM DATE (2019)
Shiflett, K., Wright, D., Karanth, A., Louri, A.: PIXEL: photonic neural network accelerator. In: HPCA 2020
Zhao, Z., Liu, D., Li, M., Ying, Z., Zhang, L., Xu, B., Yu, B., Chen, R.T., Pan, D.Z.: Hardware-software co-design of slimmed optical neural networks. In: IEEE/ACM ASPDAC (2019)
Mourgias-Alexandris, G., Totovic, A., Tsakyridis, A., Passalis, N., Vyrsokinos, K., Tefas, A., Pleros, N.: Neuromorphic photonics with coherent linear neurons using dual-IQ modulation cells. JLT. 38(4), 811–819 (2020)
Pask, C.: Generalized parameters for tunneling ray attenuation in optical fibers. J. Opt. Soc. Am. 68(1), 110–116 (1978)
Pintus, P., Hofbaurer, M., Manganelli, C.L., Fournier, M., Gundavarapu, S., Lemonnier, O., Gambini, F.: PWM-driven thermally tunable silicon microring resonators: design, fabrication, and characterization. L&P Rev. 13(9) (2019)
Bogaerts, W., Heyn, P.D., Vaerenburgh, T.V., De Vos, K., Selvaraj, S.K., Claes, T., Dumon, P., Bienstman, P., Thourhout, D.V., Baets, R.: Silicon microring resonators. L&P Rev. 6(1) (2012)
Nikdast, M., Nicolescu, G., Trajkovic, J., Liboiron-Ladouceur, O.: Chip-scale silicon photonic interconnects: a formal study on fabrication non-uniformity. JLT. 34(16), 3682–3695 (2016)
Stefan, A., Stoferie, T., Marchiori, C., Caimi, D., Czornomaz, L., Stuckelberger, M., Sousa, M., Offrein, B.J., Fompeyrine, J.: A hybrid barium titanate–silicon photonics platform for ultraefficient electro-optic tuning. JLT. 34(8), 1688–1693 (2016)
Ansys Lumerical Inc.: Ansys Lumerical HEAT. [Online]. Available: https://www.ansys.com/products/photonics/heat
Lu, L., Li, X., Gao, W., Li, X., Zhou, L., Chen, J.: Silicon non-blocking 4× 4 optical switch chip integrated with both thermal and electro-optic tuners. IEEE Photonics. 11(6) (2019)
Milanizadeh, M., Aguiar, D., Melloni, A., Morichetti, F.: Canceling thermal cross-talk effects in photonic integrated circuits. JLT. 37(4), 1325–1332 (2019)
De, S., Das, R., Varshney, R.K., Schneider, T.: Design and simulation of thermo-optic phase shifters with low thermal crosstalk for dense photonic integration. In: IEEE Access, vol. 8, (2020)
LeCun, Y., Bottou, L., Bengio, Y., Haffner, P.: Gradient-based learning applied to document recognition. In: Proceedings of the IEEE (1998)
QKeras.: https://github.com/google/qkeras
Frandsen, L.H., Ingo Borel, P., Zhuang, Y.X., Harpøth, A., Thorhauge, M., Kristensen, M., Bogaerts, W., Dumon, P., Baets, R., Wiaux, V., Woulters, J.: Ultralow-loss 3-dB photonic crystal waveguide splitter. Opt. Lett. 29(14) (2004)
Tu, Y.C., Fu, P.H., Huang, D.W.: High-efficiency ultra-broadband multi-tip edge couplers for integration of distributed feedback laser with silicon-on-insulator waveguide. IEEE Photonic J. 11(4) (2019)
Bahirat, S., Pasricha, S.: OPAL: a multi-layer hybrid photonic NoC for 3D ICs. In: IEEE/ACM ASPDAC (2011)
Jayatileka, H., Caverley, M., Jaeger, N.A.F., Shekhar, S., Chrotowski, L.: Crosstalk limitations of Microring-Resonator based WDM Demultiplexers on SOI. In: OIC 2015
Timurdogan, E., Sorace-Agaskar, C.M., Hosseini, E.S., Leake, G., Coolbaugh, D.D., Watts, M.R.: Vertical junction silicon microdisk modulator with integrated thermal tuner. In: CLEO:Science and Innovations, OSA (2013)
Güngördü, A.D., Dündar, G., Yelten, M.B.: A high performance TIA Design in 40 nm CMOS. In: IEEE ISCAS (2020)
Wang, B., Huang, Z., Sorin, W.V., Zeng, X., Liang, D., Fiorentino, M., Beausoleil, R.G.: A low-voltage Si-Ge avalanche photodiode for high-speed and energy efficient silicon photonic links. JLT. 38(12), 3156–3163 (2020)
Duong, L.H.K., Nikdast, M., Le Beux, S., Xu, J., Wu, X., Wang, Z., Yang, P.: A case study of signal-to-noise ratio in ring based optical networks-on-chip. IEEE Des. Test. 31(5) (2014)
Capra, M., Bussolino, B., Marchisio, A., Shafique, M., Masera, G., Martina, M.: An updated survey of efficient hardware architectures for accelerating deep convolutional neural networks. In: Future Internet 2020
Pisati, M., De Bernardinis, F., Pascale, P., Nani, C., Sosio, M., Pozzati, E., Ghittori, N., Magni, F., Garampazzi, M., Bollati, G., Milani, A., Minuti, A., Giunco, F., Uggetti, P., Fabiano, I., Codega, N., Bosi, A., Carta, N., Pellicone, D., Spelgatti, G., Cutrupi, M., Rossini, A., Massolini, R., Cesura, G., Bietti, I.: A sub-250 mW 1-to-56Gb/s continuous-range PAM-4 42.5 dB IL ADC/DAC-based transceiver in 7 nm FinFET. In: IEEE ISSCC 2019
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Sunny, F.P., Mirza, A., Nikdast, M., Pasricha, S. (2024). Co-designing Photonic Accelerators for Machine Learning on the Edge. In: Pasricha, S., Shafique, M. (eds) Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing. Springer, Cham. https://doi.org/10.1007/978-3-031-39932-9_10
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