Skip to main content
SpringerLink
Log in

Making a Case for Logic Locking

  • Chapter
  • First Online:
Understanding Logic Locking

  • 271 Accesses

Abstract

Due to the rising expenses and intricacy involved in the development, implementation, fabrication, and testing of modern ICs, the idea of VLSI reuse has become increasingly common in high-tech company products. While legal protection measures like patents, copyrights, contracts, trademarks, and trade secrets can safeguard companies against product misappropriation, they do not offer any physical protection to ICs. Thus, they cannot directly thwart threats such as IP piracy but can only discourage the misuse of IPs to avoid legal repercussions and financial penalties. Given the intense competition among high-tech companies and the possibility of malicious intentions in the horizontal IC supply chain, hardware designs need protection methods to safeguard against unauthorized and illegitimate access to detailed IP information. In response to these demands, several hardware design-for-trust (DfTr) techniques such as IC metering, watermarking, IC camouflaging, split manufacturing, and logic locking have been introduced. The primary objective of these techniques is to ensure that an IC is uncorrupted, trustworthy, and protected from design and data perspectives against threats such as unlawful reverse engineering and piracy. This chapter reviews these DfTr techniques in VLSI design and showcases how the versatility of logic locking could excel in IC supply chain to provide a dependable solution against a possible attacker at any point in the IC supply chain.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    A counterfeit component (i) is an unauthorized copy; (ii) does not conform to OCM design, model, and/or performance standards; (iii) is not produced by the OCM or is produced by unauthorized contractors; (iv) is an off-specification, defective, or used OCM product sold as new or working; or (5) has incorrect or false markings and/or documentation. Based on the definition above and analyzing supply chain vulnerabilities, counterfeit types could be classified into seven main groups: (1) recycled, (2) remarked, (3) overproduced, (4) out-of-spec (defective), (5) cloned, (6) forged documentation, and (7) tampered [12,13,14,15].

  2. 2.

    Relying on the same concept, different active models of protection have been introduced in the domain of logic locking [42,43,44].

References

  1. Sami, Md. S. Ul. I., Rahman, F., Farahmandi, F., Cron, A., Borza, M., & Tehranipoor, M. (2021). End-to-end secure soc lifecycle management. In 2021 58th ACM/IEEE Design Automation Conference (DAC) (pp. 1295–1298). IEEE.

    Google Scholar 

  2. Kamali, H. M., Azar, K. Z., Farahmandi, F., & Tehranipoor, M. (2022). Advances in logic locking: Past, present, and prospects. In Cryptology. ePrint Archive.

    Google Scholar 

  3. Jose, S. (2008). Innovation is at risk as semiconductor equipment and materials. In Semiconductor Equipment and Material Industry (SEMI).

    Google Scholar 

  4. Yeh, A. (2012). Trends in the global IC design service market. In DIGITIMES.

    Google Scholar 

  5. Bhunia, S., & Tehranipoor, M. (2018). Hardware security: a hands-on learning approach. Morgan Kaufmann.

    Google Scholar 

  6. Bao, C., Forte, D., & Srivastava, A. (2015). On reverse engineering-based hardware Trojan detection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(1), 49–57.

    Article  Google Scholar 

  7. Torrance, R., & James, D. (2009). The state-of-the-art in IC reverse engineering. In Cryptographic Hardware and Embedded Systems-CHES 2009: 11th International Workshop Lausanne, Switzerland, September 6–9, 2009 Proceedings (pp. 363–381). Springer.

    Google Scholar 

  8. Quadir, S. E., Chen, J., Forte, D., Asadizanjani, N., Shahbazmohamadi, S., Wang, L., Chandy, J., & Tehranipoor, M. (2016). A survey on chip to system reverse engineering. ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(1), 1–34.

    Google Scholar 

  9. Torrance, R., & James, D. (2011). The state-of-the-art in semiconductor reverse engineering. In Proceedings of the 48th Design Automation Conference (pp. 333–338).

    Google Scholar 

  10. Pawlowicz, C., Trindade, B., & Green, M. (2021). The role of cloud computing in a modern reverse engineering workflow at the 5nm node and beyond. In ISTFA 2021 (pp. 163–171). ASM International.

    Google Scholar 

  11. Asadizanjani, N., Shahbazmohamadi, S., Tehranipoor, M., & Forte, D. (2015). Non-destructive pcb reverse engineering using x-ray micro computed tomography. In ISTFA 2015 (pp. 164–172). ASM International.

    Google Scholar 

  12. Guin, U., Huang, K., DiMase, D., Carulli, J. M., Tehranipoor, M., & Makris, Y. (2014). Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain. Proceedings of the IEEE, 102(8), 1207–1228.

    Article  Google Scholar 

  13. Tehranipoor, M., & Wang, C. (2011). Introduction to hardware security and trust. Springer Science & Business Media.

    Google Scholar 

  14. Guin, U., Forte, D., & Tehranipoor, M. (2013). Anti-counterfeit techniques: From design to resign. In 2013 14th International Workshop on Microprocessor Test and Verification (pp. 89–94). IEEE.

    Google Scholar 

  15. Guin, U., DiMase, D., & Tehranipoor, M. (2014). Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead. Journal of Electronic Testing, 30, 9–23.

    Article  Google Scholar 

  16. Becker, G. T., Regazzoni, F., Paar, C., & Burleson, W. P. (2013). Stealthy dopant-level hardware trojans. In Cryptographic Hardware and Embedded Systems-CHES 2013: 15th International Workshop, Santa Barbara, CA, USA, August 20–23, 2013. Proceedings 15 (pp. 197–214). Springer.

    Google Scholar 

  17. Bhasin, S., Danger, J.-L., Guilley, S., Ngo, X. T., & Sauvage, L. (2013). Hardware Trojan horses in cryptographic IP cores. In 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography (pp. 15–29). IEEE.

    Google Scholar 

  18. Tehranipoor, M., Salmani, H., & Zhang, X. (2014). Integrated circuit authentication (vol. 10, pp. 978–983). Cham, Switzerland: Springer.

    Book  Google Scholar 

  19. Xiao, K., Forte, D., Jin, Y., Karri, R., Bhunia, S., & Tehranipoor, M. (2016). Hardware trojans: Lessons learned after one decade of research. ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 1–23.

    Article  Google Scholar 

  20. Rahman, Md. T., Forte, D., Shi, Q., Contreras, G. K., & Tehranipoor, M. (2014). CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 46–51). IEEE.

    Google Scholar 

  21. Huang, Z., Wang, Q., Chen, Y., & Jiang, X. (2020). A survey on machine learning against hardware trojan attacks: Recent advances and challenges. IEEE Access, 8, 10796–10826.

    Article  Google Scholar 

  22. Jin, Y., & Makris, Y. (2008). Hardware Trojan detection using path delay fingerprint. In 2008 IEEE International Workshop on Hardware-Oriented Security and Trust (pp. 51–57). IEEE.

    Google Scholar 

  23. Randolph, M., & Diehl, W. (2020). Power side-channel attack analysis: A review of 20 years of study for the layman. Cryptography, 4(2), 15.

    Article  Google Scholar 

  24. Longo, J., De Mulder, E., Page, D., & Tunstall, M. (2015). SoC it to EM: electromagnetic side-channel attacks on a complex system-on-chip. In Cryptographic Hardware and Embedded Systems–CHES 2015: 17th International Workshop, Saint-Malo, France, September 13–16, 2015, Proceedings 17 (pp. 620–640). Springer.

    Google Scholar 

  25. Schlösser, A., Nedospasov, D., Krämer, J., Orlic, S., & Seifert, J.-P. (2012). Simple photonic emission analysis of AES: photonic side channel analysis for the rest of us. In Cryptographic Hardware and Embedded Systems–CHES 2012: 14th International Workshop, Leuven, Belgium, September 9–12, 2012. Proceedings 14 (pp. 41–57). Springer.

    Google Scholar 

  26. Yang, B., Wu, K., & Karri, R. (2004). Scan based side channel attack on dedicated hardware implementations of data encryption standard. In 2004 International Conferce on Test (pp. 339–344). IEEE.

    Google Scholar 

  27. Kocher, P., Jaffe, J., & Jun, B. (1999). Differential power analysis. In Advances in Cryptology—CRYPTO’99: 19th Annual International Cryptology Conference Santa Barbara, California, USA, August 15–19, 1999 Proceedings 19 (pp. 388–397). Springer.

    Google Scholar 

  28. Brier, E., Clavier, C., & Olivier, F. (2004). Correlation power analysis with a leakage model. In Cryptographic Hardware and Embedded Systems-CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11–13, 2004. Proceedings 6 (pp. 16–29). Springer.

    Google Scholar 

  29. He, M., Park, J., Nahiyan, A., Vassilev, A., Jin, Y., & Tehranipoor, M. (2019). RTL-PSC: Automated power side-channel leakage assessment at register-transfer level. In 2019 IEEE 37th VLSI Test Symposium (VTS) (pp. 1–6). IEEE.

    Google Scholar 

  30. Golder, A., Das, D., Danial, J., Ghosh, S., Sen, S., & Raychowdhury, A. (2019). Practical approaches toward deep-learning-based cross-device power side-channel attack. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(12), 2720–2733.

    Article  Google Scholar 

  31. Wei, L., Luo, B., Li, Y., Liu, Y., & Xu, Q. (2018). I know what you see: Power side-channel attack on convolutional neural network accelerators. In Proceedings of the 34th Annual Computer Security Applications Conference (pp. 393–406).

    Google Scholar 

  32. Rogaway, P. (2002). Authenticated-encryption with associated-data. In Proceedings of the 9th ACM Conference on Computer and Communications Security (pp. 98–107).

    Google Scholar 

  33. WG for Design IP Encryption and Rights Management. (2015). Recommended practice for encryption and management of electronic design intellectual property (IP). In IEEE Std 1735–2014 (pp. 1–90).

    Google Scholar 

  34. Chhotaray, A., Nahiyan, A., Shrimpton, T., Forte, D., & Tehranipoor, M. (2017). Standardizing bad cryptographic practice: A teardown of the IEEE standard for protecting electronic-design intellectual property. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (pp. 1533–1546).

    Google Scholar 

  35. Anandakumar, N. N., Rahman, M. S., Rahman, M. Md. M., Kibria, R., Das, U., Farahmandi, F., Rahman, F., & Tehranipoor, M. M. (2022). Rethinking watermark: Providing proof of IP ownership in modern socs. In Cryptology. ePrint Archive.

    Google Scholar 

  36. Das, U., Muttaki, Md. R., Tehranipoor, M. M., & Farahmandi, F. (2022). ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features. In 2022 IEEE International Test Conference (ITC) (pp. 155–164). IEEE.

    Google Scholar 

  37. Abdel-Hamid, A. T., Tahar, S., & Aboulhamid, El. M. (2004). A survey on IP watermarking techniques. Design Automation for Embedded Systems, 9, 211–227.

    Article  Google Scholar 

  38. Dunbar, C., & Qu, G. (2015). A practical circuit fingerprinting method utilizing observability don’t care conditions. In Proceedings of the 52nd Annual Design Automation Conference (pp. 1–6).

    Google Scholar 

  39. Patel, H. J., Crouch, J. W., Kim, Y. C., & Kim, T. C. (2009). Creating a unique digital fingerprint using existing combinational logic. In 2009 IEEE International Symposium on Circuits and Systems (pp. 2693–2696). IEEE.

    Google Scholar 

  40. Lach, J., Mangione-Smith, W. H., & Potkonjak, M. (2001). Finger-printing techniques for field-programmable gate array intellectual property protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(10), 1253–1261.

    Article  Google Scholar 

  41. Caldwell, A. E., Choi, H.-J., Kahng, A. B., Mantik, S., Potkonjak, M., Qu, G., & Wong, J. L. (1999). Effective iterative techniques for fingerprinting design IP. In Proceedings of the 36th annual ACM/IEEE Design Automation Conference (pp. 843–848).

    Google Scholar 

  42. Kamali, H. M., Azar, K. Z., Gaj, K., Homayoun, H., & Sasan, A. (2018). Lut-lock: A novel lut-based logic obfuscation for fpga-bitstream and asic-hardware protection. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 405–410). IEEE.

    Google Scholar 

  43. Kamali, H. M., Azar, K. Z., Homayoun, H., & Sasan, A. (2019). Full-lock: Hard distributions of sat instances for obfuscating circuits using fully configurable logic and routing blocks. In Proceedings of the 56th Annual Design Automation Conference 2019 (pp. 1–6).

    Google Scholar 

  44. Kamali, H. M., Azar, K. Z., Homayoun, H., & Sasan, A. (2020). InterLock: An inter-correlated logic and routing locking. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 1–9).

    Google Scholar 

  45. Chang, C.-H., & Zhang, L. (2013). A blind dynamic fingerprinting technique for sequential circuit intellectual property protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(1), 76–89.

    Article  Google Scholar 

  46. Koushanfar, F. (2011). Integrated circuits metering for piracy protection and digital rights management: An overview. In Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI (pp. 449–454).

    Google Scholar 

  47. Herder, C., Yu, M.-D., Koushanfar, F., & Devadas, S. (2014). Physical unclonable functions and applications: A tutorial. Proceedings of the IEEE, 102(8), 1126–1141.

    Article  Google Scholar 

  48. Holcomb, D. E., Burleson, W. P., & Fu, K. (2008). Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Transactions on Computers, 58(9), 1198–1210.

    Article  MathSciNet  MATH  Google Scholar 

  49. Gassend, B., Lim, D., Clarke, D., Van Dijk, M., & Devadas, S. (2004). Identification and authentication of integrated circuits. Concurrency and Computation: Practice and Experience, 16(11), 1077–1098.

    Article  Google Scholar 

  50. Koushanfar, F., & Qu, G. (2001). Hardware metering. In Proceedings of the 38th Annual Design Automation Conference (pp. 490–493).

    Google Scholar 

  51. Alkabani, Y., Koushanfar, F., et al. (2007). Active hardware metering for intellectual property protection and security. In USENIX Security Symposium (vol. 20, pp. 1–20).

    Google Scholar 

  52. Koushanfar, F. (2017). Active hardware metering by finite state machine ob-fuscation. In Hardware Protection Through Obfuscation (pp. 161–187).

    Google Scholar 

  53. Imeson, F., Emtenan, A., Garg, S., & Tripunitara, M. (2013). Securing computer hardware using 3d integrated circuit ({IC}) technology and split manufacturing for obfuscation. In 22nd {USENIX} Security Symposium ({USENIX}Security 13) (pp. 495–510).

    Google Scholar 

  54. Garg, S., & Rajendran, J. (2017). Split manufacturing. In Hardware Protection Through Obfuscation (pp. 243–262).

    Google Scholar 

  55. Wang, Y., Chen, P., Hu, J., & Rajendran, J. J. V. (2017). Routing perturbation for enhanced security in split manufacturing. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 605–510). IEEE.

    Google Scholar 

  56. Yang, K., Botero, U., Shen, H., Forte, D., & Tehranipoor, M. (2017). A split manufacturing approach for unclonable chipless RFIDs for pharmaceutical supply chain security. In 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) (pp. 61–66). IEEE.

    Google Scholar 

  57. Usui, T., Tsumura, K., Nasu, H., Hayashi, Y., Minamihaba, G., Toyoda, H., Sawada, H., Ito, S., Miyajima, H., Watanabe, K., et al. (2006). High performance ultra low-k (k\(=\) 2.0/keff\(=\) 2.4)/Cu dual-damascene interconnect technology with self-formed MnSixOy barrier layer for 32 nm-node. In 2006 International Interconnect Technology Conference (pp. 216–218). IEEE.

    Google Scholar 

  58. Yasin, M., & Sinanoglu, O. (2015). Transforming between logic locking and IC camouflaging. In 2015 10th International Design & Test Symposium (IDT) (pp. 1–4). IEEE.

    Google Scholar 

  59. Rajendran, J., Sinanoglu, O., & Karri, R. (2013). Is split manufacturing secure? In 2013 Design, Automation & Test in Europe Conference& Exhibition (DATE) (pp. 1259–1264). IEEE.

    Google Scholar 

  60. Wang, X., Gao, M., Zhou, Q., Cai, Y., & Qu, G. (2017). Gate camouflaging-based obfuscation. In Hardware Protection Through Obfuscation (pp. 89–102).

    Google Scholar 

  61. Rajendran, J., Sam, M., Sinanoglu, O., & Karri, R. (2013). Security analysis of integrated circuit camouflaging. In Proceedings of the 2013 ACM SIGSAC Conference on Computer & Communications Security (pp. 709–720).

    Google Scholar 

  62. Collantes, M. I. M., Massad, M. El., & Garg, S. (2016). Threshold-dependent camouflaged cells to secure circuits against reverse engineering attacks. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 443–448). IEEE.

    Google Scholar 

  63. Malik, S., Becker, G. T., Paar, C., & Burleson, W. P. (2015). Development of a layout-level hardware obfuscation tool. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 204–209). IEEE.

    Google Scholar 

  64. Chen, S., Chen, J., Forte, D., Di, J., Tehranipoor, M., & Wang, L. (2015). Chip-level anti-reverse engineering using transformable interconnects. In 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (pp. 109–114). IEEE.

    Google Scholar 

  65. Shakya, B., Shen, H., Tehranipoor, M., & Forte, D. (2019). Covert gates: Protecting integrated circuits with undetectable camouflaging. IACR Transactions on Cryptographic Hardware and Embedded Systems, 86–118.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Florida, Gainesville, FL, USA

    Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi & Mark Tehranipoor

Authors
  1. Kimia Zamiri Azar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Hadi Mardani Kamali
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Farimah Farahmandi
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Mark Tehranipoor
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2024 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Zamiri Azar, K., Mardani Kamali, H., Farahmandi, F., Tehranipoor, M. (2024). Making a Case for Logic Locking. In: Understanding Logic Locking. Springer, Cham. https://doi.org/10.1007/978-3-031-37989-5_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-37989-5_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-37988-8

  • Online ISBN: 978-3-031-37989-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation