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Exploring Circuit Design Topologies for RFETs

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Design Automation and Applications for Emerging Reconfigurable Nanotechnologies

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Abstract

Designing logic gates based on emerging technologies is necessary as they form the building block for digital design. It lays the foundation to enable EDA for the commercialization of such a technology. With the emergence of reconfigurable nanotechnology as one of the viable technology for future electronics, a crucial task is to formalize designs and topologies for various logic gates and circuits (Rai et al. (Emerging Reconfigurable Nanotechnologies: Can They Support Future Electronics? In: Proceedings of the International Conference on Computer-Aided Design. ICCAD ’18. San Diego, California: ACM, 13:1–13:8, 2018)).

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Notes

  1. 1.

    While such logic gates can be realized in CMOS, due to cascading of multiple transistors between the output and \(V_{dd}\), the larger logic gates are slower in CMOS implementation.

  2. 2.

    Done in collaboration with Michael Raitza of the group.

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  1. Department of Computer Science, TU Dresden, Dresden, Germany

    Shubham Rai & Akash Kumar

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Rai, S., Kumar, A. (2024). Exploring Circuit Design Topologies for RFETs. In: Design Automation and Applications for Emerging Reconfigurable Nanotechnologies. Springer, Cham. https://doi.org/10.1007/978-3-031-37924-6_3

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  • DOI: https://doi.org/10.1007/978-3-031-37924-6_3

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