MemFlash—Floating Gate Transistors as Memristors

Abstract

The idea of resistive switching devices is originally based on the fact that the application of electric fields changes the atomic structure locally and thus also the electronic structure of the material. This leads globally to a sustained change in the resistance of the material layer, which is generally referred to as resistive switching. In resistive switching devices, these atomic reconfigurations are reversible and allow the state to be maintained for a long time, which is why the devices are referred to as memristive devices (also named Memristor). Memristive devices can be realized as two terminal devices in a metal-insulator-metal structure. In the MemFlash cell, there is no atomic rearrangement in the device and therefore is a purely electronic based switching device. The basic components of the MemFlash cell are floating gate transistors, which are reduced from a three-terminal to a two-terminal device by means of a diode-like wiring scheme and thus exhibit memristive switching behavior. In this book chapter, the MemFlash cell is introduced.

1 Introduction

Memristive devices (also called memristors) are mostly based on the effect of resistive switching. In resistive switching, the application of an electric field causes a local change in the atomic bonding structure of the crystalline atoms of the memristive layer. Resistive switching is caused by different mechanism, ranging from magnetic effects through electrostatic effects to atomic configurations. A good overview is given in [1]. Based on these effects, a number of device structures for memristive devices have been developed [2] and the research on resistive switching devices goes back to [3, 4].

Even though research on resistive switching materials goes back decades [3, 4], interest in the subject has been renewed in recent years. In this context, memristive switching materials for non-volatile memory architectures [5] and especially for neuromorphic systems [6] are considered as promising candidates. However, both of these applications require technology to manufacture memristive devices on a large scale, as well as integration or interconnection with the prevailing silicon technology [7]. The latter puts research into CMOS-compatible memristive materials and their CMOS integration at the center of research interest. This goes hand in hand with the development of CMOS integrated memristive devices [7, 8].

In this context, a MemFlash cell offer an interesting alternative to conventional memristive devices [9, 10], because it is a modified version of a floating gate transistor (FGT), which are CMOS integrable devices and commercially available. In a MemFlash cell resistive switching is caused exclusively by a pure electronic effect and not based on an atomic reconstruction.

In this chapter we will introduce the MemFlash cell. First, the concept of the MemFlash cell will be explained and it will be shown how to create a memristive device from a FGT. Subsequently, in chapter “Redox-Based Bi-Layer Metal Oxide Memristive Devices”, aspects of the MemFlash cell that are technological important will be discussed including an overview of different realizations and extensions of the basic concept. Thereafter, the range of applications for neuromorphic computing is discussed in this chapter and important properties and conditions for the cell design are presented.

2 The MemFlash Concept

Memristive devices are two-terminal devices, which in their simplest structure can be realized as a metal-insulator-metal sandwich structure. In a memristive device the resistance depends on the charge flow through in the past [11]. It was concluded that this is a fundamental property that classifies memristive devices, along with the resistor, the inductor and the capacitor, to one a fundamental device of electronics [11]. In this context, the reference to the Memristor postulated by Leo Chua already in 1971 could be drawn [12]. Even if this conclusion is critically questioned [13, 14], memristive devices or memristors show fundamental properties which cannot be reproduced with one of the other three circuit elements: common with the capacitor and the inductor is the possibility of an information storage (memory effect). However, common with the resistor, memristors are passive devices in which no energy storage takes place. The memristor is therefore, as the name suggests, a memory-resistor.

Mathematically, memristive devices can be formally represented by the following set of equations:

$$\begin{aligned} I = G(x,V,T) \cdot V \,\, with \,\, \frac{dx}{dt} = f(x,V,t), \end{aligned}$$

(1)

here x is called a state variable, which is for example a measure of the change in atomic configuration within the resistive switching material. The function f(x, V, t), describes the voltage driven changes in the atomic structure [11, 15] and is depending on the particular memristive system. The conductance of the device G(x, V, t) is named as Memductance and a simple relationship can be made between G and the state variable x via the relationship [11]:

$$\begin{aligned} G = x \cdot G_{on} + (1-x) \cdot G_{off}, \end{aligned}$$

(2)

where $G_{on}$ and $G_{off}$ are the maximum and minimum conductance of the device, respectively. Please note, that the state variable x varies between 0 and 1. However, the MemFlash cell is not based on atomic reconfigurations but is relies on the FGT. An FGT is purely function on electron charge transfer. In this context, it will be shown in the following how this device can be converted into a memristive device.

2.1 Functional Principle of a MemFlash Cell

A schematic of a simple memory transistor is shown in Fig. 1a. Basically, it consists of a MOS field-effect transistor (MOSFET) with a MOS structure (Metal Oxide Semiconductor) in whose gate stack. This MOS stack gives a memory capacitance as a gate which controls the channel of the MOSFET and is called a floating gate (FG) [16]. Depending on the charge on the FG, the vertical charge flow from source to drain through the transistor is influenced. For example, if we consider an n-MOS transistor as shown in Fig. 1a, the drain and source terminals are both heavily n-doped while the channel region is p-doped (die Bulk region könnte in der Abbildung mit p-Si versehen werden). Depending on the voltage difference between the gate electrode and the bulk junction, electrons are accumulated at the interface to the gate oxide, resulting in a conductive connection (channel) between the drain and the source junction. If the floating gate is sufficiently well isolated from its environment and the potential on the external accessible control gate is kept constant, the charge state of the floating gate defines the memory state of the transistor. However, floating gate transistors are not memristors at first glance, since memristors are two-terminal devices while the transistor essentially has three terminals—source, drain and the externally addressable control gate (cf. Fig. 1a). At this respect, the core idea of a MemFlash cell is an external circuit that allows the device to become externally a two-terminal device. A circuit that allows this is shown in Fig. 1a as well. Here, the control gate (CG) and source are combined and connected to a common potential, i.e. the ground potential. Applying a bipolar voltage signal $V_{DS}$ (see Fig. 1) the FG is charged or discharged in dependency of the bias direction via the tunneling window with the thickness $d_t$ and leads to a pinched hysteresis for $I_{DS}$ vs. $V_{DS}$ [9]. In other words, the charging or discharging of FG changes immediately the channel current $I_{DS}$.

Fig. 1

The concept a MemFlash cell: wiring scheme and I-V curve. a Schematic drawing of a MemFlash cell and the diode-like circuitry that turns a FGT into a MemFlash cell (see bold black connection between source and gate). b Typical current-voltage curve of a MemFlash cell through the circuit shown in (a). The pinched hysteresis is a fingerprint of a memristor

As shown in Fig. 1b, a pinched hysteresis loop can be realized with this connection as a fingerprint of a memristor. The current-voltage characteristic shown in Fig. 1b reflects the curve measured in Ref. [9] and describes the dependence of the channel current ($I_{DS}$) when a bipolar voltage sweep is applied to the drain contact ($V_{DS}$). Here fore, the voltage was increased linearly from zero and then decreased linearly to a negative voltage before returning to the origin (see arrows in Fig. 1b). The result is a hysteresis. In order to understand this memristive behavior more precisely, a capacitative model is developed and described in the following section.

2.2 Physical Device Model of a MemFlash Cell

The model used to describe the MemFlash cell is sketched in Fig. 2a and is taken from Refs. [9, 10]. In this capacitive model, the potential of the floating gate is expressed via

$$\begin{aligned} V_{FG} = \frac{Q_{FG}}{c_T} + k_C V_C + k_D V_D + k_B V_B \end{aligned}$$

(3)

Fig. 2

(taken from Ref. [10]. c The solid line shows the model, while the dots correspond to a real measurement. d Floating gate potential curve when a triangular voltage is applied to the drain (taken from Refs. [9, 10])

Physical model of a MemFlash device. a Equivalent circuit model of a FGT. b Different charge and discharge mechanisms for the floating gate. Current-voltage characteristics of a MemFlash cell

Here, $Q_{FG}$ is the charge stored on the floating gate, and $V_C$, $V_D$, $V_S$, and $V_B$ are the potentials of the control gate, drain, source, and bulk terminal, respectively. Furthermore, $k_C$, $k_D$, $k_S$, and $k_B$ are the respective coupling constants to the floating gate which are defined by $k_i = C_i/C_T \, (i =C, D, S, B)$. Here, $C_C$, $C_D$, $C_S$, and $C_B$ are the respective capacitances and $C_T$ is the total capacitance given by $C_T =C_C +C_D +C_S +C_B$. In the memristive mode, as already mentioned, a three-terminal floating gate transistor is reconfigured to a two-terminal cell. Therefore, the control gate and source potentials are grounded. If we also neglect coupling to the bulk, the floating gate potential equation reduces to the following form:

$$\begin{aligned} V_{FG} = \frac{Q_{FG}}{c_T} + k_D V_D \end{aligned}$$

(4)

Thus, the floating gate potential is determined by the drain voltage $V_D$ and by the charge on the floating gate $Q_{FG}$, which in turn is determined by $V_D$ and can be calculated by

$$\begin{aligned} Q_{FG} = Q_{FG}(t_0) + \int _{t_0}^{t_{1}} I_t(V_D,V_{FG})dt \end{aligned}$$

(5)

Here, $I_t (V_D,V_{FG})$ is the current that charges or discharges the $F_G$ through the tunnel window (the tunnel window is marked by a capacitance Ct in circuit model in Fig. 2a). In general, there are different contributions to that current, but the main current contributions come from the Fowler–Nordheim tunnel effect and from the injection of hot charge carriers [10]. These two effects are outlined in Fig. 2b. In the case of Fowler–Nordheim tunneling, the application of a high electric field effectively thins the thickness of the tunnel oxide, leading to the tunneling of electrons. While hot charge carrier injection is a thermally generated charge transport mechanism in which charge carriers can overcome the potential barrier between drain and floating gate at high voltages. Both mechanisms can be described within analytical equations and are represented in the model shown in Fig. 2 over two current sources [10]. Here, the Fowler–Nordheim current is given by

$$\begin{aligned} I_{FN} = \pm A_{tox} \cdot A_{FN}\cdot (E_{tox})^2 \ exp(-B_{FN}/E_{tox}) \end{aligned}$$

(6)

where $A_{tox}$ is the tunneling oxide area, and $A_{FN}$ and $B_{FN}$ are the Fowler–Nordheim tunneling constants. $E_{tox}$ is the electrical field during programming and erasing, $E_{tox} = (V_D - V_{FG})/d_{tox}$, and depends on the thickness of the tunneling gate oxide $d_t$. According to Ref. [10] the equation for the hot carrier injection current can be approximated by

$$\begin{aligned} I_{inj} = \pm A_{tox} \cdot A_{inj} \ exp \Bigl ( - \frac{B_{inj}}{(c_{inj}+V_{FG})^2} + D_{inj} \cdot V_D \Bigr ) \end{aligned}$$

(7)

where $A_{inj}$, $B_{inj}$, $C_{inj}$ and $D_{inj}$ are positive fit constants, which have to be estimated from experimental data. In order to describe the current-voltage characteristics with the equations, a theoretical description of the MOSFET is still missing. This can best be described by the following set of equations:

$$\begin{aligned} I_D = \left\{ \begin{array}{cllll} \frac{1}{2} \beta \left[ (V_G - V_{th}) V_D - \frac{V_D^2}{2} \right] \cdot (1 + \lambda V_D) &{} for &{} V_G> V_{th} &{} and &{} V_D< V_G - V_{th}\\ \frac{1}{2} \beta (V_G - V_{th})^2 \cdot (1+ \lambda V_D) &{} for &{} V_G> V_{th} &{} and &{} V_D > V_G-V_{th}\\ 0 &{} for &{} V_G < V_{th} &{} &{} \end{array} \right. \end{aligned}$$

(8)

Here $V_{th}$, $\beta$ and $\lambda$ are the threshold voltage, transconductance and channel length modulation parameter of the MOS transistor, respectively. $V_G$ is the gate potential, which is equal to $V_D - V_{FG}$ for $V_D < 0$ and $V_G = V_{FG}$ for $V_D>0$. Figure 2c shows the current-voltage characteristic calculated with the model by using a linear triangular voltage sweep and the following set of parameters: $\lambda$ = 0.0625 $\text {V}^{-1}$, $\beta$ = 28.3 $\upmu$S$\text {V}^{-1}$ and $V_{th} = 1.052$ V. In addition, Fig. 2c compares the model with a typical experimental I-V curve.

Due to the good agreement between modeled and measured I-V characteristics, the physical function mechanism can be well described via the model: for positive drain voltage, the floating gate charge is reduced, while for negative voltages, the QFG is charged. This changes the channel resistance from the high resistance state (HRS) to the low resistance state (LRS) for positive drain voltages and vice versa from LRS to HRS for negative voltages. The associated change in floating gate potential is shown in Fig. 2d and demonstrates that by changing the voltage at the drain terminal, the floating gate potential can be varied. This forms the kernel of the MemFlash cell’s memristive behavior and thus the charge on the floating gate can be identified as the memristive state variable x, where the following relationship holds:

$$\begin{aligned} \frac{dx}{dt} = f(x,V,t) \rightarrow \frac{d Q_{FG}}{dt} = I_t (G_{FG}, V_D, V_{FG}) \end{aligned}$$

(9)

Furthermore, the dynamic function f in the case of the MemFlash cell can be represented by the charge current of the floating gate. This allows the memristive behavior to be adjusted directly via the charge transport mechanism of the floating gate and thus to tailor the cell for its application. The latter will be described in more detail below.

3 Technology and Scaling Issues of the MemFlash

A major advantage of MemFlash cells over most of the conventional Memristors is their compatibility with CMOS technology. The floating gate transistor described in the previous chapters was manufactured in a NMOS technology and is thus already present in an established technology [17]. This enables the production of large numbers of memristive cells with low variability and high yield. This is crucial for the application of Memristors in neuromorphic computing and remains one of the major challenges of conventional Memristor technologies. However, as shown in the last paragraph, in the MemFlash cell the memristive behavior is mainly described by the tunnel current for charging and discharging the floating gate. This places a special technological emphasis on the tunnel oxide and the associated requirements in terms of storage duration and transport mechanisms. This defines the technological parameters for the current-voltage characteristics of the MemFlash cell and will be discussed in the following section. In addition, it will be shown that the concept of the MemFlash cell is not limited to FGTs, but can be applied to different types of thin film junction-less memory transistors in general. This offers a wide range of technological possibilities to tailor the behavior of the MemFlash cell for particular application.

3.1 Tunneling Oxide Scaling

Memory transistors from the last section, in the form of the EEPROM (electrically erasable programmable read-only memory) cell, form the basis of today’s non-volatile storage media such as flash memory. These memory transistors are manufactured using the floating gate tunneling oxide (FLOTOX) technology shown in Fig. 3a [16]. Within this technology, the gate oxide is thinned at the drain connection so that electrons can pass through the tunneling oxide via the transport processes described in the last section. This changes the charge on the floating gate, but depends on a number of factors, including programming time (the longer the time, the greater the change), temperature (the higher the temperature, the fewer hot electrons are available for injection), tunneling oxide quality and imposes stringent conditions on the programming voltage required. In particular, a higher voltage amplitude and larger programming times are required compared to Memristors, whose resistor switching mechanism is based on atomic reconfiguration. Thus, the technological factor that plays the leading role here is the tunnel oxide thickness, which is chosen in such a way that the memory cell allows information storage for more than 10 years [10, 17]. However, in a number of applications, such as neuromorphic computing, short storage times are acceptable or even desirable and the required voltage of the MemFlash cell can be reduced accordingly by decreasing the layer thickness [10].

An estimation of the drain voltage for different film thicknesses was made in Ref. [10] and the main results are shown in Fig. 3. Obviously, by reducing the film thickness, the required voltage can be significantly reduced to below 10 V (see black data points in Fig. 3b), while still maintaining relatively strong resistance changes as depicted as $R_{off}/R_{on}$ in Fig. 3b (see red data points). Furthermore, the maximum current is also significantly reduced (see inset in Fig. 3b), which leads to a significant reduction in the power consumption of the cell [10].

Fig. 3

(Figures are taken from Ref. [10])

Scaling of tunneling oxide layer: a the thickness of the gate oxide $d_t$ has a significant influence on the voltage required and thus on the power consumption. b Dependence of $V_D$ and the maximum change in resistance $R_{off}/R_{on}$ on the thickness of the tunnel oxide. c Simplified schematic representation of the effective tunneling regime via the Fowler–Nordheim tunneling process. No charge or discharge was assumed for tunnel currents smaller than $10^{-19}$ A. An electric field strength of 12 MV cm$^{-1}$ was used for the breakdown condition. d Retention of the memory cell. Shown here via the change in the floating gate potential as a function of the layer thickness.

In addition, the effective intervals for a charge transport between drain and FG were estimated in Ref. [10]. In this case, the voltage interval is limited by the breakdown field strength of $\text {SiO}_2$ to large voltages, while the use of a too low voltage leads to the fact that no change can be achieved at the floating gate. As shown in Fig. 3c, this interval becomes smaller for quite thin oxide thicknesses. It has been found that oxide thicknesses in the range of 4–5 nm lead to a required voltage at the drain between 4 and 5 V for FGTs [10]. However, these values lead to quite short storage times, as shown in Fig. 3d, and thus rule out a broad application of the MemFlash cell in this form. Nonetheless, the concept of the MemFlash cell can be applied to different types of memory transistors. In the following section, this issue will be discussed in more detail.

3.2 Different Types of MemFlash

Figure 4 gives an overview of different MemFlash cell designs. Besides the MemFlash cell which is based on a floating gate transistor (labeled as FLOTOX in Fig. 4), SONOS (silicon oxide nitride oxide polysilicon) transistors [18], quantum dot devices [19] and also memory transistors with a gate which splits into a y geometry [20] have been realized so far. In the following section, these other types of MemFlash cells will be briefly discussed.

Fig. 4

Different memory transistors used as MemFlash device: these include floating-gate oxide (FLOTOX) transistors [9], silicon oxide nitride oxide polysilicon (SONOS) field-effect transistors [18], transistors with a Y-gate [19], and quantum dot (QD) floating gate transistors [20]

In Ref. [18], the MemFlash concept was applied to industrially manufactured SONOS field-effect transistors. To account for the special characteristics of depletion-type SONOS transistors, the two-terminal wiring of the MemFlash cell was extended to include a resistance-bridged pn diode. Common SONOS devices have very thin layers of the ONO gate stack, with an approximate thickness of 2 nm for the tunnel oxide (O), 5–10 nm for the nitride layer (N), and 5 nm for the barrier oxide (O) toward the gate electrode. Thus, this type of MemFlash cells promise reliable operation, low parameter spread and high integration density [18].

A completely different approach was taken in Ref. [19]. Here a MemFlash cell was realized with a quantum dot (QD) floating gate transistor by shorting the source contact of the quantum wire (QW) and lateral gates. Here, the memristive behavior arises from the Coulomb interaction of localized QD charges with the nearby QW. This leads to a change in conductance that depends on the voltage polarity.

Finally, an energy-efficient memristive floating-gate device was presented in Ref. [20]. This device was fabricated in a standard 180 nm CMOS process and connected to a readout transistor. This concept, known as a Y-flash cell, allows the device to operate in an energy-efficient subthreshold memristive mode. This allows small signal changes to be linearized, so that a dynamic resistance range of two orders of magnitude can be achieved. This allows 65 discrete resistance levels to maintain long data retention, high endurance and a low noise margin.

An extension of a memory transistor by another transistor was proposed in Ref. [21]. The idea of this approach is to combine a MemFlash based on a complementary n-MOS transistor/p-MOS transistor arrangement, similar to conventional CMOS inverters (not shown in Fig. 4). This concept, called C-MemFlash, allows the voltage polarity and the direction of the resistor switching to be adjusted by means of an appropriate wiring scheme.

4 MemFlash Cells for Neuromorphic Computing

One of the increasingly important areas of application for Memristors is neuromorphic computing [22]. Here, Memristors are used to emulate synaptic plasticity, i.e. the changes in coupling strengths between neurons. In neuronal networks, synapses play a special role, since these variable changes enable local and decentralized information processing. Thus, synaptic plasticity is a basic building block for learning and memory processes in neuronal networks and a detailed modeling is required to achieve functional neuronal networks [23]. A large number of different models that mimics neuronal learning are known, whereby the theory of Hebbian learning models allows a quite extensive description of these [24]. In the following, the possible applications of MemFlash cells in the field of neuromorphic computing will be presented in the context of this model.

4.1 Hebbian Learning Models

Hebbian learning models goes back to a rule postulated by Donald Hebb in 1949 [25] which states that “neurons that fire together wire together.” This means that neurons that are simultaneously active change their connection strength also named as synaptic weight. This learning rule can be easily translated into a mathematical framework by denoting the change in the coupling strength is defined by a function which describes the activities $A_j$ or $A_i$ of the adjacent neurons, i.e. the pre- and post-synaptic neurons, and the actual weight of the synapse $\omega _{ij}$ [26]:

$$\begin{aligned} \frac{d \omega _{ij}}{dt} = F(\omega _{ij}, A_j, A_i) \end{aligned}$$

(10)

In the simplest case the function $F(\omega _{ij}, A_j, A_i)$ can be written as:

$$\begin{aligned} F(\omega _{ij}, A_j, A_i) = \alpha A_j \cdot A_i \end{aligned}$$

(11)

Here, the coefficient $\alpha$ is called learning rate and is usually positive: $\alpha > 0$. A learning rule with $\alpha < 0$ is usually called anti-Hebbian [26]. However, the exciting question is how this learning theory can be applied to the MemFlash cell. Here, a structural similarity between the equation for the change of the synaptic weight $\omega _{ij}$ and the change of the memristive state x can directly be recognized, which allows us to derive the following relation [27]:

$$\begin{aligned} \frac{d \omega }{dt} \rightarrow \frac{dx}{dt} \rightarrow \frac{d Q_{FG}}{dt} = I_t(Q_{FG},V_D,V_{FG}) \end{aligned}$$

(12)

Thus, the change in synaptic coupling strength can be directly modeled by the change in floating-gate charge [24, 27].

Furthermore, the learning function $F(\omega _{ij}, A_j, A_i)$ is simulated via the tunnel current and the pre- and postsynaptic activities can be identified as the potentials at the drain and floating gate. For this purpose, voltage pulse trains at the drain terminal can be used, as sketched in Fig. 5a, which must be adjusted in their voltage level, pulse length and frequency to emulate the desired learning behavior. An example that emulates the change of synaptic weight via the conductance of the MemFlash cell is shown in Fig. 5b. Here, constant frequency pulse trains of 175 10 V set pulses (also called potentiation pulses) and 175 −7.5 V reset pulses (also called depression pulses) were used, which were varied in their pulse width. A read pulse of +2.5 V was consecutively applied after each potentiation/depression pulse to non-destructively readout the channel conductance. Figure 5c shows the normalized synaptic weight changes $\omega (t)$ (floating-gate charges) for the different pulse widths. Here, a strong nonlinearity of the weight change in the respective first potentiation and depression pulses can be observed. An exception is the 5 ms curve, which shows no unlearning behavior. This result can also be seen from the curves shown in Fig. 5d. Good agreement with a variety of biological plasticity processes has been discussed in Ref. [24]. The application of cellular learning paradigms in the area of associative learning was also demonstrated in [24]. In addition, a broad range of applications of Y-gate MemFlash cells for neuromorphic architectures was presented in Ref. [20].

Fig. 5

(Figure b–d are taken from [24])

Application of MemFlash cell in neuromorphic computing: a replication of synaptic plasticity as a change in FG charge. For this purpose, the floating gate charge can be adjusted by suitable pulse trains at the drain potential and thus the conductance of the MemFlash cell. b an example of an emulated plasticity curve from Ref. [24]. This shows a strong non-linear behavior in the change of conductance (c). d The learning rates are thus initially very high and become lower with the number of pulses.

5 Conclusion

In summary, it can be stated that by means of defined charge changes of the floating gate, controlled learning models can be realized in hardware. In addition, the existing technology integration of MemFlash cells with the associated good reproducibility and high production capability of a large number of cells offers a good possibility for the realization of neuromorphic computing architectures in hardware.