Redox-Based Bi-Layer Metal Oxide Memristive Devices

Abstract

In a memristor or a so-called memristive device, the resistance state depends on the previous charge flow through the device. The new resistance state is stored and classifies a memristor as a non-volatile memory device. This likewise unique and simple feature qualifies memristive devices as attractive compartments with regard to the development of a universal memory and beyond von Neumann computing architectures, including in-memory computing and neuromorphic circuits. In this chapter, we present studies on two kinds of bi-layer metal oxide memristive devices with the layer sequences Nb/NbO$_{\textrm{z}}$/Al$_2$O$_3$/Nb$_{\textrm{x}}$O$_{\textrm{y}}$/Au and TiN/TiO$_\textrm{x}$/HfO$_\textrm{x}$/Au, either prepared by reactive DC-magnetron sputtering, etching and optical lithography. It is shown that the memristive properties of such devices can be engineered, which enables tailoring of the memristive devices for particular applications.

1 Introduction

The term “Memristor” is a portmanteau from the two words “Memory” and “Resistor”. A memristor (also called a memristive device) typically consists of capacitor-like layer sequences, i.e., a metal-insulator-metal structure. A universal property of the memristive device concept is that the memristive state depends on previously induced charge flows, applied currents, or applied electric fields, which result in different stored resistance states. This simultaneously unique and simple device principle, together with the predicted potential for breakthrough technologies in areas such as universal memories and novel non-Boolean computing schemes for cognitive electronic systems, drives the research and development of memristors and memristor-based circuits. Memristive devices were intensively studied in the last century’s sixties and seventies [1,2,3]. The field was further driven forward by the establishment of the theoretical background of memristors by Leon Chua (1971), with the corresponding experimental realization and interpretation by the Hewlett-Packard (HP)-Labs (2008) [4, 5].

Currently, two main development avenues can be explored for memristive devices. The first focuses on resistive random access memories (RRAMs). It is believed that the zoo of today’s existing memory diversity can be replaced by a single (universal) memory concept. RRAMs are considered attractive candidates for universal memories because they: show non-volatile data storage, can be densely integrated, are fast, and are cheap to produce. In particular, such a universal memory might attenuate the problem known as memory latency in modern digital computers [6, 7]. Besides the RRAM goal, which may be categorized under the label “More Than Moore”, novel and very appealing computer architectures have been proposed in which memristors might play a vital role. Another main spotlight of possible memristive device applications may be assigned to such catchphrases as non-Boolean computing, bio-inspired information processing, neuromorphic engineering, or cognitive electronics [8,9,10,11,12,13,14,15,16]. On the local synaptic level, learning in nervous systems is explained by the Hebbian learning rule [17] and, amongst others, spike-timing dependent plasticity (STDP) [18]. STDP and other memory-related mechanisms observed in nervous systems, such as long term potentiation (LTP) and long term depression (LTD) [19], were successfully mimicked by memristive devices [8, 20,21,22]. To what extent larger networks of memristive devices can mimic higher brain functions is still unknown.

Until now, a huge number of experimental findings on memristor devices consisting of a wide variety of metal/insulator material combinations have been published, all of which show memristive $I\text {-}V$ curves [23]. For details concerning resistive switching and the underlying physical-chemical mechanisms, we refer the reader to the overwhelming literature on the subject [12, 14, 23,24,25,26,27]. These physical-chemical mechanisms include electronic effects (e.g., charging of electron traps) [25, 26], magnetic effects (e.g., spin-transfer torque - STT) [28] or ferroelectricity (e.g., ferroelectric tunnel junctions - FTJ) [29]. Moreover, nano-ionic mechanisms are widely utilized to build memristive devices. Included are phase change memory (PCM) devices [30] in which the resistance of the active layer is modulated by switching between crystalline and amorphous phase. Moreover, devices based on the formation and dissolution of conductive filaments composed of metal ions, i.e., the electrochemical metalization effect (ECM) [31], or composed of oxygen vacancies, i.e., the valance change mechanism (VCM) [23, 32], belong to this class. Furthermore, VCM can also be realized without conductive filaments. In these interface-based memristive devices, the resistance is changed by modulating interfacial properties like the Schottky-barrier height [24, 32,33,34] or the tunneling probability [35,36,37] by the movement of oxygen vacancies or oxygen ions [23, 25]. Thus, the functionality of VCM devices is based on redox reactions. A sketch of a filamentary-based device and an interface-based device are shown in Fig. 1a and b, respectively. This chapter deals with VCM devices composed of bi-layer metal oxides.

Fig. 1

Schematic illustrations of VCM devices based on filament formation (a) and homogeneous ion movement (b)

Since the requirements the devices have to fulfill depend on the application, both types of devices are investigated for different purposes, as described in more detail in chapter https://doi.org/Neuromorphic Circuits with Redox-Based Memristive Devices and in further literature [23, 38,39,40,41]. In this respect, filamentary-based devices are available in a more mature technology compared to interface-based devices [41]. However, the need for an initial electro-forming step, a current compliance for switching, a pronounced intrinsic randomness of the switching process, and a limited amount of achievable resistance states are some drawbacks compared to interface-based devices [24, 38,39,40,41,42]. On the other hand, endurance, retention, switching speed, and scalability are some of the reported benefits of filamentary devices [38,39,40,41,42]. The properties of interface-based devices will be discussed in further detail in Sect. 2 while the properties of filamentary-based devices are described in Sect. 3.

The quality of the solid-state electrolyte, in which ion movement occurs, determines the switching properties. In this regard, it has been theoretically shown that an oxygen-deficient HfO$_{\textrm{x}}$ with x between 1.5 and 1.75 is required for the most efficient nucleation of vacancies as the starting point for filament growth [43]. Park et al. [44] experimentally verified this by showing that $x = 1.8$ leads to filamentary switching while $x = 1.98$ leads to interface-based switching. However, stoichiometric HfO$_2$ matrices are also reported to show filamentary switching enabled through local reduction to HfO$_{\mathrm {2-x}}$ [45, 46]. Similar observations are reported for Sr$_2$TiO$_4$ [47]. However, in these devices, only the filament-type switching is explained by the movement of vacancies. In contrast, the interface-based switching is explained by the charging and discharging of electron traps. Moreover, it has been shown that the oxygen content in HfO$_{\textrm{x}}$ [44, 45] and TaO$_\textrm{x}$ [48] can be used to modify important device parameters in filamentary devices, such as forming and switching voltages, memory window, and high resistance state (HRS) and low resistance state (LRS) currents. Furthermore, adjusting the switching window by tailoring the defect density has also been reported for interface-based devices in simulation studies [44, 49]. Engineering device properties will be discussed in more detail in Sect. 4. The second oxide in the bi-layer system can have different functions, like acting as an oxygen reservoir or a diffusion barrier. A reservoir like TiO$_{\textrm{x}}$ [50, 51], TaO$_{\textrm{x}}$ [37], or a TiON formed at a TiN electrode interface [52, 53] allows to increase or decrease oxygen vacancy or ion concentration in the solid-state electrolyte while performing memristive switching. On the other hand, a diffusion barrier like Al$_2$O$_3$ [54,55,56,57] restricts ion movement within the electrolyte and, thus, can improve retention times [55] or switching linearity [56], and can lead to multi-state operation [56, 57]. It should be noted here that bi-layer metal oxide memristive devices are not necessarily switching by ion migration. As a second switching mechanism, the charging and discharging of electron traps are reported to be responsible for memristive switching in metal oxide junctions [58,59,60,61,62,63].

Both interface-based and filamentary-based VCM devices consisting of bi-layer metal oxides are described in the following, and exemplary realizations are shown in Sects. 2 and 3, respectively. Strategies to engineer the electrical parameters of these memristive devices to meet the requirements for specific applications are provided in Sect. 4.

2 Interface-Based Devices

The current transport is homogeneously distributed across the electrode area in interface-based memristive devices. Here, the resistance is determined by the interfacial properties of the incorporated materials. Thus, the resistance change is based on altering interfacial properties like Schottky-barrier height or width [24, 32,33,34] or tunneling probability [35,36,37]. This is achieved by a rearrangement of oxygen vacancies or oxygen ions [23, 25] or by charging and discharging electron traps [58,59,60, 62]. In that way, interface-based memristive devices show analog, i.e., gradual switching [24, 35, 41]. Moreover, no electro-forming is needed, and devices with a high $I\text {-}V$ non-linearity [33, 64] to avoid the need for additional selector elements for passive crossbar integration [65] are reported. Furthermore, the intrinsic randomness is less pronounced than in filamentary devices [38, 41]. Moreover, interface-based VCM devices have already been integrated into 3D stacks in complementary metal-oxide-semiconductor (CMOS) technology with a minimum feature size of 5 nm [64]. However, CMOS integration and scaling to the nanoscale is challenging for most reported devices [41]. CMOS integration is challenging if the incorporated materials or the needed deposition steps are not used in CMOS fabrication lines or if the used materials do not withstand the CMOS fabrication steps. This is explained in detail in chapter Integration of Memristive Devices into a 130 nm CMOS Baseline Technology. Downscaling is challenging because the resistance of interface-based devices scales with the electrode area, and most reported devices have high resistances even on the micrometer scale. Drawbacks are, furthermore, a worse retention time and slower switching speed [41] compared to filamentary devices. Therefore, interface-based devices are good candidates to emulate synapses in bio-inspired neuromorphic networks [11, 40], as described in detail in chapter Neuromorphic Circuits with Redox-Based Memristive Devices. Two different devices are described in this section. The first device is based on a Nb$_{\textrm{x}}$O$_{\textrm{y}}$/Al$_2$O$_3$ bi-layer in which Nb$_{\textrm{x}}$O$_{\textrm{y}}$ acts as the solid-state electrolyte while Al$_2$O$_3$ is a diffusion barrier restricting ion movement in the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ layer [55]. The second device is based on a HfO$_2$/TiO$_{\textrm{x}}$ bi-layer. Here, TiO$_{\textrm{x}}$ acts as an oxygen reservoir, enabling an oxygen exchange with HfO$_2$ [44].

Fig. 2

b, f are reprinted from [55] (licensed under CC BY 4.0), c is adapted from [55] (licensed under CC BY 4.0), and d, e are reprinted from [68] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

Double barrier memristive devices (DBMDs). a Schematic material stack. b Typical $\left|J \right|\text {-}V$ hysteresis curve. c Area-dependent current transport in HRS (red) and LRS (blue). d Optical microscope photography of a $16 \cdot 16$ crossbar array containing DBMDs. e Typical $\left|I \right|\text {-}V$ curves of a crossbar-integrated device (red) and a single device (black). f Retention of a DBMD (black) and a device without an Al$_2$O$_3$ layer.

2.1 Devices Based on Nb$_{\textrm{x}}$O$_{\textrm{y}}$/Al$_2$O$_3$

The first device is named double barrier memristive device (DBMD) [55]. The double oxide layer Nb$_{\textrm{x}}$O$_{\textrm{y}}$/Al$_2$O$_3$ is sandwiched between an Au top electrode and an Nb bottom electrode, as it is sketched in Fig. 2a. The Au leads to a Schottky barrier formation, while alumina acts as a tunnel barrier. The movement of oxygen ions within Nb$_{\textrm{x}}$O$_{\textrm{y}}$ under an applied electric field is reported to be responsible for memristive switching [55, 66], as modeled by a kinetic Monte Carlo simulation [67] which is explained in more detail in chapter Modeling and Simulation of Silver-Based Filamentary Memristive Devices. It should be noted that the charging and discharging of electron traps as the switching mechanism cannot be ruled out [55]. However, a variation in the charge distribution within Nb$_{\textrm{x}}$O$_{\textrm{y}}$ leads to both a variation of the Schottky-barrier height and effective tunneling width. By scaling the solid-state electrolyte down to 2.5 nm, i.e., to the length scale of a single electron wave, the impact of the bulk resistance is minimized, and a very strong mutual interdependency of both barriers is achieved. Thus, both interfaces are altered simultaneously when the charge distribution varies.

Devices with active areas between 70 $\upmu \textrm{m}^2$ and 2500 $\upmu \textrm{m}^2$ are produced on 100 mm Si wafers, which are passivated by a thermal SiO$_2$ layer. All layers are deposited by DC magnetron sputtering in one and the same vacuum chamber without breaking the vacuum. The devices are structured using standard optical lithography in combination with lift-off and etching steps. Additional passivation with SiO$_{\textrm{x}}$ enables the deposition of Ti metal contact pads, which allow an automatic measuring of device properties across the whole wafer. This will be discussed in more detail in Sect. 4.1. The fabrication process is explained in detail in [55, 66]. First, Nb and Al are deposited in an Ar atmosphere. The subsequent deposition of Nb$_{\textrm{x}}$O$_{\textrm{y}}$ from a metallic target in an Ar/O2 atmosphere leads to the fully oxidation of Al to Al$_2$O$_3$, as observed in electron energy loss spectroscopy (EELS) and energy-dispersive X-ray spectroscopy (EDX) in a transmission electron microscope (TEM) [69]. The Nb$_{\textrm{x}}$O$_{\textrm{y}}$ stoichiometry was found to be between the oxidation states $\textrm{Nb}_{\textrm{2}}\textrm{O}_{\textrm{5}}$ and $\textrm{Nb}_{\mathrm {}}\textrm{O}_{\textrm{2}}$. All interfaces but the Nb/Al$_2$O$_3$ interface appeared to be smooth on the nanoscale. Due to the roughness at the lower interface, the thinnest parts of the alumina were determined to be 1.3 nm, as sketched in Fig. 2a. Furthermore, the interface between the Nb bottom electrode and Al$_2$O$_3$ was also slightly oxidized. The TEM measurements, including EELS and EDX, are described in more detail in chapter Critical Discussion of Ex situ and In situ TEM Measurements on Memristive Devices.

Figure 2b shows a typical current density versus voltage ($J\text {-}V$) hysteresis curve of a DBMD, which was measured with a grounded Nb electrode, while voltage was applied to the Au electrode. Switching from HRS to LRS is taking place gradually, i.e., in an analog way, by applying a positive voltage to the Au top electrode. Switching back to HRS takes place by applying a negative bias to the top electrode. No initial electro-forming is needed, and an intrinsic current compliance is present. Both HRS and LRS show an area-dependent current transport, as shown in Fig. 2c, since the product of device area A and resistance R results in a constant value for both states. The absolute value of the current density is depicted on a log scale in Fig. 2b, showing the high $J\text {-}V$ non-linearity and asymmetry. For dense device integration in a crossbar array, a selector device in series to every memristive element or a strong built-in $I\text {-}V$ non-linearity is needed to avoid parasitic currents, i.e., the sneak path problem, when addressing a specific device [65, 70]. The built-in diode-like characteristics of DBMDs allows crossbar integration without needing additional selector devices [68]. A photograph of a crossbar array consisting of 256 DBMDs is shown in Fig. 2d. Here, the devices are located at the cross points of the metallization lines. In that way, each top and bottom contact pad connects the top electrodes in one column of the array. Each left and right pad connects the bottom electrodes of one row. Thus, only 32 contact pads are needed to address all 256 memristive devices. The $I\text {-}V$ characteristics of crossbar integrated devices are similar to those of reference devices, as shown in Fig. 2e, in which the black line belongs to a reference device and the red line to a crossbar-integrated device, respectively. Furthermore, Fig. 2f shows the retention time of a DBMD. After the device was set from $R_{off}$ (HRS) to $R_{on}$ (LRS), the resistance was recorded every 60 s with a voltage pulse of 0.5 V amplitude and 2 s duration. In that way, a non-destructive read-out of the resistance state was performed, and the relaxation of the state was measured. The resistance increased fast in the first 600 s (black data points), while afterward, the resistance change was significantly less pronounced. An $R_{on}/R_{off}$ ratio of more than one order of magnitude was still present after one day. This behavior can be quantitatively described by fitting the experimental data to a $\sim t^\beta$ power law (red lines) [61]. In the first 600 s, the relaxation can be described by $\sim t^{0.65}$, while afterward, $\sim t^{0.18}$ holds. That two different power laws are dominant for different time intervals suggests that different physical processes may be responsible for memristive switching, e.g., charging of traps and movement of ions on a faster and slower timescale, respectively. It is also shown in Fig. 2f that the Al$_2$O$_3$ considerably affects the retention time. The grey squares show the same measurement on devices without alumina. The retention characteristics of those devices show no resistance increase for the first 700 s but a steep increase afterward fitted by a $\sim t^{2.3}$ power law. Thus, the Al$_2$O$_3$ does significantly increase the retention time. Furthermore, the fact that alumina acts as a diffusion barrier for oxygen [54, 56, 57] is also believed to lead to the self-limited switching behavior due to the limited amount of oxygen ions within Nb$_{\textrm{x}}$O$_{\textrm{y}}$ and no oxygen exchange between both oxides.

The retention time of DBMDs does not allow to use these devices for classical memory applications but for neuromorphic circuits [11]. Bio-inspired learning of visual patterns utilizing crossbar integrated DBMDs as hardware synapses have already been demonstrated [68]. This is explained in chapter Neuromorphic Circuits with Redox-Based Memristive Devices in detail. However, the drawbacks of DBMDs are those named above for interface-based devices [41]. In this respect, the scalability is challenging due to the high resistance, even on the micrometer scale. For quadratic devices with a feed size of 10 $\upmu \textrm{m}$, the current in HRS for a typical read-out voltage of 0.5 V is in the pA range. Thus, for scaling the devices down to the nanoscale, the resistance has to be tailored by orders of magnitude. On the other hand, high ohmic devices are desired for low-power applications. Thus, the resistance has to be adjusted so that currents are high enough to be suitable for electronic circuits but low enough to account for energy efficiency. Strategies for engineering device performances are given in Sect. 4. Furthermore, compatibility with CMOS technology is crucial for developing integrated circuits. While Al₂O₃ is a well-known dielectric in CMOS technology, Nb$_{\textrm{x}}$O$_{\textrm{y}}$ in the needed stoichiometry might be more challenging to be integrated into state-of-the-art fabrication lines. Moreover, gold is not desired in CMOS fabrication. Also, the impact of other fabrication steps (e.g., tempering in back-end-of-line processes [71]) has to be considered. CMOS integration of memristive devices is explained in chapter Integration of Memristive Devices into a 130 nm CMOS Baseline Technology. However, if CMOS integration is not possible, devices can be fabricated directly onto CMOS processed substrates in other fabrication lines [72, 73].

After describing device performance, including benefits and drawbacks of the introduced DBMDs, the model for current transport and memristive switching is explained in more detail in the following. Figure 3a shows an equivalent circuit emulating the $I\text {-}V$ characteristics [55, 66]. Here, the Au/Nb$_{\textrm{x}}$O$_{\textrm{y}}$ interface is modeled as a Schottky diode $D_s$, the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ is modeled as a parallel circuit of a resistor $R_{NbO}$ and a capacitor $C_{NbO}$, and the Al$_2$O$_3$ layer is modeled as a voltage-controlled current source $I_t$ emulating elastic tunneling in parallel to a capacitor $C_{AlO}$. The variable describing the memristive state x denotes the average ion position within the Nb$_{\textrm{x}}$O$_{\textrm{y}}$. More precisely, thermionic emission theory was employed to model the Schottky diode [74, 75]. According to this theory, charge carriers have enough energy due to an applied electric field to cross the potential barrier between a metal and a semiconductor. For an applied forward bias V, this current can be calculated by

$$\begin{aligned} I_S = I_R\left( e^{\frac{qV}{nk_{B}T} } -1 \right) , \end{aligned}$$

(1)

Fig. 3

©2016 IEEE. Reprinted, with permission, from [M. Hansen et al., IEEE International Conference on Rebooting Computing (ICRC) (2016)]

Model of a DBMD [66] a Equivalent circuit b Schematic of the band diagram.

where q is the elemental charge, $k_B$ is the Boltzmann constant, T is the temperature, and n is the ideality factor. If $n > 1$, deviation from ideal thermionic emission theory is indicated. This deviation can be caused by, e.g., additional tunneling through the barrier (thermionic field emission), additional interface states, or barrier in-homogeneity [74, 75]. The reverse current $I_R$ is given by

$$\begin{aligned} I_R = A^{*}AT^2e^{-\frac{\Phi _B}{k_{B}T} }. \end{aligned}$$

(2)

Here, $A^{*}$ is the effective Richardson constant, A is the device area, and $\Phi _B$ is the Schottky barrier height. For reverse bias, however, and if the apparent barrier height $\Phi _B$ is reasonably smaller than the band gap of the insulator, the reverse current decreases gradually with the applied negative bias. This can be described by

$$\begin{aligned} I_{R, V<0} = -A^{*}AT^2 e^{-\frac{\Phi _B}{k_{B}T}}e^{-\frac{\alpha _r \sqrt{ \left|V \right|}}{k_{B}T}}. \end{aligned}$$

(3)

The device-dependent parameter $\alpha _r$ is used to fit the experimentally observed reverse voltage dependency. As it is described in [55], the Schottky diode dominates the current transport for voltages below 0.5 V (LRS) and 1.0 V (HRS). For higher voltages in the forward regime, i.e., higher positive voltages on the Au electrode, the Al$_2$O$_3$ tunnel barrier gets relevant and acts as in intrinsic current compliance. The tunneling current can be modeled by the Simmons equation [76]

$$\begin{aligned} I_{tun} = \frac{ KA }{ d_{tox}{^2}}\left[ x_1{^2}e^{\left( -\alpha d_{tox}x_1\right) }- x_2{^2}e^{\left( -\alpha d_{tox}x_2\right) }\right] . \end{aligned}$$

(4)

In Eq. 4 holds $x1 = \sqrt{ \Phi - e V_I/2}$ and $x2 = \sqrt{ \Phi + e V_I/2}$. Here, $\Phi$ is the tunnel barrier height, and $V_I$ is the resulting voltage across the tunnel barrier. Furthermore, A is the device area, K is a constant value, $d_{tox}$ is the barrier thickness, and $\alpha = 2 \sqrt{ 2m }/ \hbar$ (m: free electron mass; $\hbar$: Planck’s constant divided by $2\pi$).

As it is indicated in Fig. 3a, the Schottky barrier height $\Phi _B$, the effective tunnel barrier width $d_{eff}$ (corresponds to $d_{tox}$ in Eq. 4) as well as the resistance of Nb$_{\textrm{x}}$O$_{\textrm{y}}$ $R_{NbO}$ are dependent on the state variable x, i.e., on the average ion position. Thus, redistribution of oxygen ions within the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ leads to a change in the interfacial properties of the Schottky barrier and the tunnel barrier, while the resistance of Nb$_{\textrm{x}}$O$_{\textrm{y}}$ is only slightly affected [55]. Details about the evolution of x under applied bias and the impact on the interfacial properties can be found in [55, 66]. This model was adapted by Dirkmann et al. [67]. Here, a lumped element circuit model containing the Schottky diode and the tunnel barrier is consistently coupled with a 3D kinetic Monte Carlo model for the ion transport. The simulation results show that the drift of charged oxygen ions within the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ can account for resistive switching behavior. In that way, a Schottky barrier height lowering from 0.90 eV to 0.83 eV, a decrease of the ideality factor from 4.0 to 3.4, and a decrease of the effective tunnel barrier thickness from 1.3 nm to 1.2 nm were determined to explain the $R_{on}/R_{off}$ ratio of more than one order of magnitude. The model also covers the retention behavior. Furthermore, the simulation indicates that the whole applied voltage drops across the Schottky barrier for reverse bias and low forward bias, while the tunnel barrier is responsible for the built-in current compliance at higher forward biases. The model is also described in more detail in chapter Modeling and Simulation of Silver-Based Filamentary Memristive Devices. A sketch of the band diagram for HRS and LRS is given in Fig. 3b and shows the decrease of the Schottky barrier height as well as the tunnel barrier width for switching from HRS to LRS [66].

Fig. 4

Reprinted from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

Interface-based TiN/TiO$_\textrm{x}$/HfO$_\textrm{x}$/Au device. a Typical $\left|I \right|\text {-}V$ hysteresis curve. b Schematic material stack with indicated switching model. Red and blue spheres indicate mobile oxygen ions and stationary oxygen vacancies, respectively. c Equivalent circuit d Retention of interface-based devices (red) and filamentary devices (blue).

2.2 Devices Based on HfO$_2$/TiO$_{\textrm{x}}$

Another device based on the oxide bi-layer HfO$_2$/TiO$_{\textrm{x}}$ sandwiched between an Au top electrode and a TiN bottom electrode is discussed now [44]. All used materials but the Au are already integrated into CMOS fabrication lines [77]. A typical $I\text {-}V$ characteristic for a device with an area of 100 $\upmu \textrm{ m}^2$ is shown in Fig. 4a with grey dots. The switching mechanism is reported to be similar to that of the DBMDs. A Schottky barrier is formed between Au and HfO$_2$. Mobile oxygen ions within HfO$_2$ lead to resistive switching, as sketched in Fig. 4b, c. However, as for the DBMDs, charging and discharging of electron traps cannot be omitted as a reason for switching [44]. The $I\text {-}V$ characteristics are qualitatively similar to the DBMDs. Thus, gradual and electro-forming free switching for voltages exceeding a certain threshold and a high $I\text {-}V$ non-linearity leading to a diode-like behavior are present. However, one difference is that a current compliance of 10 $\upmu \textrm{ A}$ is used for switching to prevent dielectric breakdown. Furthermore, the switching window, i.e., the difference between HRS and LRS, decreases with increasing device area. This leads to the fact that the HRS shows an area-dependent current transport while the LRS seems to be not area dependent. However, as it is described in detail in [44], the drift velocity of oxygen ions is modeled to be area dependent, which leads to less switching for increasing device areas and thus to a decreased $R \cdot A$. The retention time can be fitted with a power law function of $\sim t^{0.3}$, depicted in Fig. 4d by the red dots.

The devices are produced with DC magnetron sputtering of all materials without breaking the vacuum and subsequent standard optical lithography and edging steps on 100 mm Si wafers passivated with thermal SiO$_2$. Device areas between 100 and 2500 $\upmu \textrm{ m}^2$ are fabricated on one and the same wafer. One clear advantage of this material system is that the stoichiometry of HfO$_2$ can easily be adjusted during sputtering. A HfO$_{1.98}$, which is named HfO$_2$ in this chapter for simplicity reasons, leads to the described device performance, while HfO$_{1.8}$ leads to filamentary-based switching, which is covered by Sects. 3 and 4.2.

The device model shown in Fig. 4c contains a Schottky diode formed between Au and HfO$_2$, which is described by thermionic emission theory (see Eqs. 1–3). The oxides are both modeled by parallel RC circuits. The model described in detail in [44] reproduces the $I\text {-}V$ characteristics very well, as depicted in Fig. 4a by the red solid line. Here, the resistive switching is dominated by Schottky-barrier height decreasing from 0.71 eV to 0.61 eV and the ideality factor increasing from 3.9 to 4.45 by considering oxygen ion movement as switching mechanism. The model also covers the decreasing $R \cdot A$ with increasing A.

3 Filamentary-Based Devices

Many transition metal oxide-based memristive devices show resistive switching associated with filamentary-type VCM [23, 32, 78]. VCM is triggered by the migration of field-assisted oxygen ion-related defects in transition metal oxides. The oxygen ion-related defects are typically oxygen vacancies that are much more mobile than the transition metal cations [79]. The oxygen vacancy migration and valence change of the cation sub-lattice often appear in the form of the formation and dissolution of a conductive filament in a localized area in the oxide leading to filamentary-type switching.

The resistive switching is typically observed after an initial electro-forming step in filamentary-type devices [79]. Double-positively charged oxygen vacancies ($V_0^{++}$) are generated by electro-forming, and the $V_0^{++}$s migrate under the applied electric field. If $V_0^{++}$s are close to each other, a single charged state ($V_0^{+}$) becomes more favorable. The cluster of $V_0^{+}$s are arranged in a filament structure, where the $V_0^{+}$ has a significantly higher energy barrier for diffusion than $V_0^{++}$ [80]. The localized conductive filament leads to reversible changes of local resistivity and overall device resistance [81]. The vacancies located in the filament have a high diffusion energy barrier. Therefore, the filamentary-type devices typically show long retention properties.

The bi-layer metal oxide devices typically consist of an oxygen vacancy reservoir layer and a solid-state electrolyte layer for filamentary-type memristive devices [82]. Under an applied electric field, oxygen vacancies are injected into the solid-state electrolyte from the reservoir layer. The oxygen vacancies form a localized conductive filament in the electrolyte layer, which reduces the overall resistance. If the electrolyte layer builds a Schottky-like barrier at the interface to the contacting metallic electrode, the conductive filament leads to a lowering of the barrier height and, thus, the overall device resistance [50]. The filamentary devices can be recognized by the resistance-area product [83]. The resistance in the ON state (LRS) is independent of the electrode area size because the conductive filament is created in a localized form.

The benefits of filamentary RRAM devices are manifold. These devices can show a high endurance, high retention time, a fast switching speed (up to ns regime), and great scalability in the nm regime [38,39,40,41,42]. Moreover, they have already been integrated into CMOS technology, allowing to combine traditional electronic circuits with RRAM devices on the very same chip [77, 84,85,86,87], and even 3D integration has been shown [84, 88, 89]. Drawbacks are the need for an initial electro-forming step and a current compliance for switching, the need for selector devices to integrate them in memory arrays, pronounced intrinsic randomness of the switching process, a limited amount of achievable resistance states, and a rather low resistance [38,39,40,41,42, 65, 70]. However, a bi-layer metal oxide concept has recently attracted attention to tackle the intrinsic randomness issue in filamentary devices [57]. Besides, randomness can be exploited for certain tasks [90, 91]. Moreover, even though most RRAM devices can only be switched between two resistance states (binary devices), multilevel devices have already been reported. For this multi-state operation, a variable current compliance for switching to LRS and a variable switching voltage for switching to HRS are usually needed [45, 52, 92,93,94], or variable pulse widths can be used [45]. However, devices showing a gradual switching with identical pulses have also been reported [56, 95]. Moreover, more sophisticated programming algorithms are reported to reach specific resistive states[57, 85, 87, 88, 94, 96, 97].

In this section, a TiO$_{\textrm{x}}$-HfO$_{\textrm{x}}$ bi-layer oxide device is mainly presented as an example of a filamentary-based VCM memristive device [44]. Using the TiO$_{\textrm{x}}$-HfO$_{\textrm{x}}$ bi-layer oxide device, typical electrical characteristics of filamentary-based devices are shown.

The TiO$_{\textrm{x}}$-HfO$_{\textrm{x}}$ memristive devices consist of TiN(50 nm) as the bottom electrode, TiO$_{\textrm{x}}$(30 nm)/$\textrm{HfO}_{\textrm{x}}$(2-8 nm) metal oxide bi-layers, and Au(50 nm) as the top electrode. The devices were fabricated on a 4-inch wafer, where the devices have 6 different active area sizes with a thickness gradient of the HfO$_{\textrm{x}}$ layer from 2 nm to 8 nm. This 4-inch wafer fabrication process enables to exclude wafer-to-wafer variability, and study the effect of the area size and the thickness of HfO$_{\textrm{x}}$ on the electrical properties of the memristive devices.

In Fig. 5, the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ bi-layer memristive devices show a typical $I\text {-}V$ curve as a filamentary-type device. At first, an electro-forming step was required to initiate the resistive switching in the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ memristive device. The electro-forming process was characterized by an abrupt jump in the current at a higher voltage (2.3 V) than the SET/RESET voltages. However, a high voltage through electro-forming could make it difficult for memristive devices to be integrated into CMOS circuits. Strategies to overcome this issue are already reported [45, 98, 99] and are addressed in Sect. 4.2.

After the electro-forming cycle, the resistive switching is observed in the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ memristive device. The switching required external current compliance of 5 mA for the SET process, while the RESET exhibited a compliance-free behavior. Bipolar switching properties were observed, and the amplitudes of switching voltages were symmetric, with −0.7 V and 0.7 V for SET and RESET, respectively. The TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device featured gradual switching characteristics, while typical filamentary type devices show an abrupt SET process. The origin of the abrupt transition during SET is related to positive feedback between the current increase and Joule heating [100]. In order to achieve a gradual switching behavior, a layer stack modification [100] and a multi-layer stack approach [51] have been proposed. In the multi-layer stack concept, for example, the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ bi-layer oxide can be exploited, where TiO$_{\textrm{x}}$ serves as a reservoir for oxygen vacancies and stabilizes the switching process [57]. A gradual switching can promote uniformity during device operation. Furthermore, a gradual resistance transition during both SET and RESET is favorable for analog computing applications [101].

Fig. 5

$I\text {-}V$ curve obtained by DC voltage sweep measurement showing RS and electro-forming in the filamentary TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ devices

Fig. 6

b is reproduced from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

a A train of 20 set voltage pulses and the subsequent 20 reset voltage pulses. A non-linear transition from the SET to the RESET is observed. b Linear trend in the resistance change in dependency on the amplitude of the switching pulse voltage. c Multi-state in the SET and d in the RESET resulting from the adjusted amplitude of switching voltages.

Gradual switching is often related to analog behavior. The analog behavior can be investigated using pulse measurements, applying a train of voltage pulses to memristive devices. Figure 6a shows the switching behaviors of the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device in a pulse measurement. For the measurement, 20 SET voltage pulses followed by 20 RESET voltage pulses are applied, while a reading pulse is applied after each switching pulse to read the resistance of the device. The TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device shows a non-linear transition from the SET to the RESET, as shown in Fig. 6a. However, the magnitude of resistance change is influenced by the amplitude of the applied switching voltage pulses in Fig. 6c, d. The impact of pulse amplitude is observed by applying switching voltage pulses with varied amplitude, each followed by 200 reading pulses. Furthermore, the median values of resistance were extracted from Fig. 6c, d, and the resistance change from the initial state was calculated at each switching voltage amplitude. The resistance change showed symmetry in Fig. 6b between the SET and the RESET operation. Symmetric and analog resistive switching is desirable for neuromorphic computing since this makes the programming of the memristive device more efficient [102].

Another indication of the filamentary-type device can be the retention property. In Fig. 4d, the retention property of the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device is compared to the interface-type device described in Sect. 2. The interface-type device has the same material configuration but fewer oxygen vacancies in the HfO$_{\textrm{x}}$ layer ($x = 1.98$). The filamentary-type device shows a much longer retention time than the interface-type device due to the high diffusion barrier of the vacancies within the filament. This has been quantitatively shown by fitting the retention measurement to the $\sim t^\beta$ power law [61] introduced in Sect. 2, leading to $\beta = 0.02$ compared to $\beta = 0.3$ for the interface-based devices. Thus, the relaxation of the resistance is proceeding orders of magnitude slower in the filamentary devices.

4 Engineering $I\text {-}V$ Characteristics of Memristive Devices

The possibility of adapting electrical parameters of memristive devices allows engineering the device performance to meet the requirements for specific applications [45, 49]. Parameters such as switching voltage, forming voltage, HRS, LRS, the switching dynamics, or the number of resistance states can be engineered. Typical strategies are tailoring the switching oxide itself by adjusting the stoichiometry or the density of oxygen vacancies or ions [44, 45, 47,48,49], doping with additional cations [94], or using different oxide phases [91, 94]. Furthermore, adding additional oxide layers to affect the oxygen exchange [55,56,57] or the local temperature distribution [51] can impact the memristive behavior. Geometrical parameters like the switching oxide thickness [44, 71] or the device area [44, 55] can also influence the $I\text {-}V$ characteristics. In Sect. 4.1, strategies for tailoring the interface-based devices introduced in Sect. 2 are described. This includes a thorough analysis of the process plasma during sputter deposition of DBMDs. Section 4.2 deals with engineering approaches to tailor the filament-based devices shown in Sect. 3.

4.1 Engineering of Interface-Based Devices

The devices described in Sect. 2 are fabricated by magnetron sputtering [103, 104]. The thin film deposition conditions like pressure, gas composition, structure and strength of the magnetic field, amplitude and form of discharge, and substrate position and orientation strongly influence electrical and optical material properties [105,106,107,108,109]. In this respect, gas flow rates and the resulting pressure significantly impact particle energies and, thereby, the structure and density of deposited films [106, 107]. Furthermore, the gas composition affects chemical reactions in the gas phase and at surfaces (target, substrate), influencing, e.g., the stoichiometry. Moreover, the substrate position and orientation relative to the sputter target affect film properties since particle fluxes and electric potentials in the plasma environment can show strong spatial in-homogeneity due to, e.g., structure and strength of the involved magnetic field [105, 107,108,109]. Another crucial parameter during reactive sputter deposition in an electronegative gas like $\mathrm {O^2}$ is the density of negatively charged ions. If the target surface gets completely poisoned, negative oxygen ions are formed and accelerated by the electric field towards the substrate. This can cause defects or stress in deposited materials due to the high kinetic energy [105, 110]. The radial distribution, the energy, and the impinging angle of these ions depend on the erosion of the target (i.e., the target geometry) and the discharge voltage. It has been shown that the erosion state of a target can be correlated with the resistivity of oxides, attributed to the impact of negatively charged oxygen ions [105, 111]. The erosion is almost only taking place in a ring-shaped area (called race track) determined by the magnetic field.

Fig. 7

Reprinted from [49] [F. Zahari et al., Journal of Vacuum Science & Technology B 37, 061203 (2019)], with the permission of AIP Publishing

Electrical characterization of DBMDs at different positions on a 100 mm wafer: a Resistance map measured with 1.6 V. b Device resistance dependent on radial position for positive bias (black dots) and negative bias (red squares). c–f) Typical $\left|J \right|\text {-}V$ curves at different radial positions 1 to 4 (−25 mm, $+$5 mm, $+$30 mm, and $+$35 mm).

To correlate the plasma properties to the electrical characteristics of DBMDs, several plasma parameters of the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ deposition process were measured at different positions underneath the Nb target since the $I\text {-}V$ characteristics vary at different positions on the 100 mm wafer [49]. Figure 7 shows the device-to-device variation across the whole wafer. Figure 7a contains a resistance map measured with read-out voltages of 1.6 V on a spatial resolution of 1 mm, showing circular symmetry. Here, 5336 devices with an area of 400 $\upmu \mathrm {m^2}$ were measured. Figure 7b depicts the dependence of the resistance for positive (black dots) and negative (red squares) bias on the radial position. Therefore, the resistances of up to ten devices were averaged for each position. Defective devices (short-circuited or not properly connected to the wiring) and test structures [gray squares in Fig. 7a] were not used for averaging. In the inner area of the wafer with a radius of about 25 mm, current rectification is observed, and the devices show memristive behavior as described in Sect. 2. However, not only the resistance but also the switching window varies with position, as can be seen by comparing Fig. 7c with d. The yellow ring in Fig. 7a, starting at about 30 mm away from the center, contains devices with relatively high resistance. The $I\text {-}V$ characteristics differ significantly from the functional devices in the center [Fig. 7e]. No rectification and no hysteresis can be observed. Here, the race track of the target is located. In the outer red area in Fig. 7a, the resistance is rather low and comparable to the resistance in the inner area. However, no rectification and no hysteresis are apparent [Fig. 7f]. It should be noted that $I\text {-}V$ curves with lower voltages are depicted in Fig. 7e, f because the devices suffer dielectric breakdown for higher voltages at these locations.

Fig. 8

Reprinted from [49] [F. Zahari et al., Journal of Vacuum Science & Technology B 37, 061203 (2019)], with the permission of AIP Publishing

Plasma parameters in dependency on the radial position. a Energy flux b Electron temperature, c Floating potential of probe d Plasma potential e Current of positive ions. In a–e, the mean values and the standard deviations determined with two measurements for each position (three for the center position) are depicted (squares with error bars). The solid and dashed lines show fits of the mean values. Results obtained with a target to probe distance of 60 mm and 80 mm are shown in red (squares/solid lines) and blue (squares/dashed lines), respectively.

As described above, devices located at different positions on a 100 mm wafer show significant different $I\text {-}V$ characteristics even though they were produced in one and the same process. Thus, the DBMDs are well suited to correlate plasma process parameters with material properties and, finally, with electrical properties [49]. The overall goal is first to understand the impact of several plasma parameters on the electrical properties and second to use these findings to develop a process to fabricate plasma-engineered devices tailored for specific applications. Thus, plasma parameters were recorded with a probe consisting of a sensor copper plate (11 mm in diameter) connected at the backside to a thermocouple for temperature measurement (40 $\upmu$V/K) and a copper bias wire [109]. This was used as a passive thermal probe (PTP) [109, 112] and as a Langmuir probe (LP) [113, 114]. A PTP is used to measure the energy balance at the location of the sample. The energy flux is dominated by impinging particles, surface reactions, incoming radiation, and loss processes such as heat conduction and convection through the surrounding gas and by emitted radiation [106]. Therefore, the energy balance depends on the process parameters named above, and it has a crucial impact on film properties [106, 107, 115]. The energy balance during Nb$_{\textrm{x}}$O$_{\textrm{y}}$ deposition at different positions is shown in Fig. 8a. With an LP, on the other hand, additional process parameters like the electron temperature $T_{e}$ [Fig. 8b], the floating potential of the probe $\Phi _{fl}$ [Fig. 8c], the plasma potential $\Phi _{pl}$ [Fig. 8d], and the current density of positively charged ions to the probe $j_{ion}$ [Fig. 8e] are measured by applying a voltage sweep to the bias wire and evaluating the measured current [116, 117]. While the energy flux and $j_{ion}$ show a Gaussian distribution with maxima in the center as expected for an unbalanced magnetron, the other parameters show a more complex dependency on the position. In particular, $T_{e}$ and $\Phi _{pl}$ have local maxima at the location of the race track, while $\Phi _{fl}$ has local minima approx. 20 mm away from the center, where the devices show the largest switching window and the lowest resistance for positive bias together with a pronounced rectification [compare Fig. 7a–d]. Thus, it is expected that the effect of the energy balance superimposes with the other plasma parameters and with the distribution of negatively charged oxygen ions to obtain a Nb$_{\textrm{x}}$O$_{\textrm{y}}$ film having properties (e.g., oxidation state and defect concentrations) as needed for memristive switching in DBMDs. This knowledge can potentially be exploited for engineering device performance by using multiple frequency capacitively coupled plasmas (MFCCPs) for sputter deposition. An MFCCP allows to control the ion energy and the ion flux independently of one another during sputtering and thus can help to control different process parameters [118, 119].

To show the influence of the plasma parameters on the stoichiometry of Nb$_{\textrm{x}}$O$_{\textrm{y}}$, TEM/EELS measurements were performed on two different devices, one located at a radial position of 5 mm (showing memristive behavior) and one at a radial position of −30 mm (showing relatively high resistance and no switching), respectively [49]. While Nb$_{\textrm{x}}$O$_{\textrm{y}}$ of the functional device is in a high oxidation state between $\textrm{Nb}_{\textrm{2}}\textrm{O}_{\textrm{5}}$ and $\textrm{Nb}_{\mathrm {}}\textrm{O}_{\textrm{2}}$, as already shown before [69], the Nb$_{\textrm{x}}$O$_{\textrm{y}}$ from the non-functional device shows significantly less incorporated oxygen and cannot be assigned to one of the known niobium oxidation states (i.e., $\textrm{Nb}_{\textrm{2}}\textrm{O}_{\textrm{5}}$, $\textrm{Nb}_{\mathrm {}}\textrm{O}_{\textrm{2}}$, or $\textrm{Nb}_{\mathrm {}}\textrm{O}_{\mathrm {}}$). Furthermore, the film thickness does vary only by 0.1 nm between both positions and thus within the standard deviation of the TEM measurement. The deviation in film thickness does not explain the substantial deviation in $I\text {-}V$ characteristics since devices with both thicknesses lead to memristive switching devices if they are located within the center of the wafer. Thus, the deviations of the $I\text {-}V$ characteristics can be mainly attributed to the chemical and electronic properties of the niobia, while the geometrical properties are less important. This can indeed be correlated to the plasma process parameters. Moreover, the kinetic Monte Carlo simulations [67] introduced in Sect. 2 were extended to show the impact of the concentration of the mobile charged defects on the switching window [49]. The results are depicted in Fig. 9a. In particular, it is shown that an increase in defect concentration $n_d$ from $2 \cdot 10^{20} \textrm{cm}^{-3}$ to $8 \cdot 10^{20} \textrm{cm}^{-3}$ increases the switching window at 0.5 V from a factor of approx. 3 to a factor of approx. $4 \cdot 10^{5}$. Thus, increasing the defect concentration by a factor of 4 does lead to an increased switching window by five orders of magnitude. Increasing ion concentration in the interface-based HfO$_{\textrm{x}}$/TiO$_{\textrm{x}}$ device also leads to a larger switching window shown by simulations [44]. Furthermore, as it is shown in Fig. 9b, also the voltage range in which a hysteresis loop can be observed changes with ion concentration, and the reverse current is also more affected as in the model of the DBMDs.

Fig. 9

Modeled hysteresis curves dependent on the mobile defect concentration. a $\left|J \right|\text {-}V$ curves of DBMDs. Reprinted from [49] [F. Zahari et al., Journal of Vacuum Science & Technology B 37, 061203 (2019)], with the permission of AIP Publishing. b $\left|I \right|\text {-}V$ curves of interface-based TiN/TiO$_\textrm{x}$/HfO$_\textrm{x}$/Au device. Reprinted from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

Fig. 10

Reprinted from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

Tailoring of the electro-forming voltage in the filamentary TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ devices by tuning the HfO$_{\textrm{x}}$ thickness.

Fig. 11

Impact of the oxygen vacancy concentration on the switching hysteresis determined by simulations. Reprinted from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/). a Concentration of oxygen vacancies and resistive switching behavior. b Switching window as a function of the concentration of the oxygen vacancies

Fig. 12

Reprinted from [44] (licensed under CC BY 4.0, https://creativecommons.org/licenses/by/4.0/)

TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device variability dependent on the product of the active area and the HfO$_{\textrm{x}}$ thickness.

4.2 Engineering of Filamentary-Based Devices

This section presents methodologies to engineer the characteristics of the filamentary-type memristive devices, such as electro-forming, $I\text {-}V$ non-linearity, retention, and variability. In particular, engineering methods for the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ memristive devices, that are presented in Sect. 3, are further described.

The concentration of oxygen vacancies in the metal oxide is one of the decisive parameters for the filamentary-type switching behaviors [43]. In the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ memristive device, the HfO$_{\textrm{x}}$ showed a substoichiometric property of $x = 1.8$ in X-ray photoelectron spectroscopy (XPS) measurements. The HfO$_{\textrm{x}}$ layer had an optimal environment for efficient electro-forming and filamentary-type switching [43]. In the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ devices, oxygen deficiency in the HfO$_{\textrm{x}}$ was achieved by deliberately growing a substoichiometric oxide film using a wedge sputtering method. Another approach to modifying the oxygen vacancies in the oxide layer is inserting an oxygen scavenging metal layer [120]. As already stated above, adjusting the vacancy concentration is a common way to adjust electrical switching parameters like forming voltage or switching voltages [45, 48, 98, 99]. Another method for scaling the forming voltage is tuning the thickness of the metal oxide layer. In Fig. 10, the electro-forming voltage in the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device showed a dependency on the thickness of the $\textrm{HfO}_{\textrm{x}}$. The thicker the switching oxide layer, the higher the voltage required to initiate resistive switching.

Besides impacting forming and switching voltages, the vacancy concentration also affects the switching hysteresis. In Fig. 11a, the simulation result shows such an impact on the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device. There is an optimum concentration of oxygen vacancies at $2.5 \cdot 10^{26}$ m$^{-3}$, where the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ device has the maximum switching window at a read-out voltage of −0.1 V, shown in Fig. 11b. The simulation shows that the device suffers from a higher concentration of oxygen vacancies due to the threshold value of oxygen diffusion [44].

Formation and dissolution of filaments are stochastic processes, which means the filamentary-type devices typically show a high variability during the switching. However, scaling the active area size down can reduce the variability [120]. Moreover, the study of the TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ filamentary devices shows that the variability can be influenced by the correlation between the thickness of the oxide layer and the active area size. As shown in Fig. 12, an optimal combination of the oxide thickness and the active area size exists to obtain reliable switching operation.

The comparison of the retention time of interface-based and filamentary-type TiO$_{\textrm{x}}$/HfO$_{\textrm{x}}$ devices [see Fig. 4d] implies that the modification of oxygen deficiency in the HfO$_{\textrm{x}}$ layer can control the retention property. In this respect, many studies show methods to enhance the retention time by introducing retention stabilization layers to modify the oxygen deficiency [54, 121].