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Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells

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Designing Modern Embedded Systems: Software, Hardware, and Applications (IESS 2022)

Part of the book series: IFIP Advances in Information and Communication Technology ((IFIPAICT,volume 669))

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Abstract

Modern processors experience memory contention when the speed of their computational units exceeds the rate at which data can be accessed in memory. This phenomenon is well known as the memory bottleneck and is a great challenge in computer engineering. In order to mitigate the memory bottleneck in classic multi-core architectures, a scalable parallel computing platform called Grid of Processing Cells (GPC) has been proposed. To evaluate its effectiveness, we model the GPC using SystemC TLM-2.0, with a focus on memory contention. As an example, we parallelize an APNG encoder application and map it to the GPC and compare its performance to traditional shared memory processors. Our experimental results show improved execution times on the GPC due to a large decrease in memory contention.

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Correspondence to Vivek Govindasamy .

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Govindasamy, V., Arasteh, E., Dömer, R. (2023). Minimizing Memory Contention in an APNG Encoder Using a Grid of Processing Cells. In: Henkler, S., Kreutz, M., Wehrmeister, M.A., Götz, M., Rettberg, A. (eds) Designing Modern Embedded Systems: Software, Hardware, and Applications. IESS 2022. IFIP Advances in Information and Communication Technology, vol 669. Springer, Cham. https://doi.org/10.1007/978-3-031-34214-1_9

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  • DOI: https://doi.org/10.1007/978-3-031-34214-1_9

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-34213-4

  • Online ISBN: 978-3-031-34214-1

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