Skip to main content

Exploiting Heterogeneity in PIM Architectures for Data-Intensive Applications

  • Conference paper
  • First Online:
Designing Modern Embedded Systems: Software, Hardware, and Applications (IESS 2022)

Part of the book series: IFIP Advances in Information and Communication Technology ((IFIPAICT,volume 669))

Included in the following conference series:

  • 175 Accesses

Abstract

The scaling of common architectures for data-intensive applications is limited by the memory wall issues that culminate in energy and performance losses. Near-data or Processing in Memory (PIM) approach has been revisited to tackle this problem, along with a wide variety of architectural designs. However, these devices commonly rely on Application Specific Integrated Circuit (ASIC) designs, which in turn fail to cover the heterogeneity found in such applications. This paper discusses and exploits the heterogeneity present in the data-intensive realm by using a range of permutations for the tuple (algorithm, dataset, programming language). Relying on commonplace hardware performance metrics, we show how to identify the main changes in the processing demands and select the best near-data configuration. Using the proposed strategy, one could see a performance difference of 1.52x, and an Energy Delay Product of 2.86x in the studied examples.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 99.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Ahn, J., Hong, S., Yoo, S., Mutlu, O., Choi, K.: A scalable processing-in-memory accelerator for parallel graph processing. In: Proceedings of the 42nd Annual International Symposium on Computer Architecture, pp. 105–117 (2015)

    Google Scholar 

  2. Alves, M.A., Diener, M., Santos, P.C., Carro, L.: Large vector extensions inside the hmc. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1249–1254. IEEE (2016)

    Google Scholar 

  3. Azarkhish, E., Rossi, D., Loi, I., Benini, L.: Design and evaluation of a processing-in-memory architecture for the smart memory cube. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schröder-Preikschat, W., Teich, J. (eds.) ARCS 2016. LNCS, vol. 9637, pp. 19–31. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-30695-7_2

    Chapter  Google Scholar 

  4. Cass, S.: The top programming languages: Our latest rankings put python on top-again-[careers]. IEEE Spectr. 57(8), 22–22 (2020)

    Article  Google Scholar 

  5. Dennard, R.H., Gaensslen, F.H., Yu, H.N., Rideout, V.L., Bassous, E., LeBlanc, A.R.: Design of ion-implanted mosfet’s with very small physical dimensions. IEEE J. Solid-State Circuits 9(5), 256–268 (1974)

    Article  Google Scholar 

  6. Drumond, M., et al.: The mondrian data engine. ACM SIGARCH Comput. Architect. News 45(2), 639–651 (2017)

    Article  Google Scholar 

  7. Gonçalves, L.R., Moura, R.F.D., Carro, L.: Aggressive energy reduction for video inference with software-only strategies. ACM Trans. Embedded Comput. Syst. (TECS) 18(5s), 1–20 (2019)

    Article  Google Scholar 

  8. Ike-Nwosu, O.: Inside the python virtual machine (2015)

    Google Scholar 

  9. Ismail, M., Suh, G.E.: Quantitative overhead analysis for python. In: 2018 IEEE International Symposium on Workload Characterization (IISWC), pp. 36–47. IEEE (2018)

    Google Scholar 

  10. Kent, W.J., et al.: The human genome browser at ucsc. Genome Res. 12(6), 996–1006 (2002)

    Article  Google Scholar 

  11. Lee, Y.: Risc-v “rocket chip" soc generator in chisel. In: Online slides (2015). https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-chip-generator-workshop-jan2015.pdf

  12. de Lima, J.P.C., Santos, P.C., Alves, M.A., Beck, A.C., Carro, L.: Design space exploration for pim architectures in 3d-stacked memories. In: Proceedings of the 15th ACM International Conference on Computing Frontiers, pp. 113–120 (2018)

    Google Scholar 

  13. Nair, R., et al.: Active memory cube: a processing-in-memory architecture for exascale systems. IBM J. Res. Dev. 59(2/3), 1–17 (2015)

    Article  Google Scholar 

  14. Okamoto, K.: What is being done with open government data? an exploratory analysis of public uses of new york city open data. Webology 13(1) (2016)

    Google Scholar 

  15. O’Loughlin, D., Coffey, A., Callaly, F., Lyons, D., Morgan, F.: Xilinx vivado high level synthesis: Case studies (2014)

    Google Scholar 

  16. Pawlowski, J.T.: Hybrid memory cube (hmc). In: 2011 IEEE Hot Chips 23 Symposium (HCS), pp. 1–24. IEEE (2011)

    Google Scholar 

  17. Pugsley, S.H., et al.: Ndc: Analyzing the impact of 3d-stacked memory+ logic devices on mapreduce workloads. In: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 190–200. IEEE (2014)

    Google Scholar 

  18. Redmon, J., Farhadi, A.: Yolov3: An incremental improvement. arXiv preprint arXiv:1804.02767 (2018)

  19. Rossi, R.A., Ahmed, N.K.: An interactive data repository with visual analytics. SIGKDD Explor. 17(2), 37–41 (2016). http://networkrepository.com

  20. Santos, P.C., de Lima, J.P., de Moura, R.F., Alves, M.A., Beck, A.C., Carro, L.: Enabling near-data accelerators adoption by through investigation of datapath solutions. Int. J. Parallel Prog. 49(2), 237–252 (2021)

    Article  Google Scholar 

  21. Santos, P.C., Oliveira, G.F., Tomé, D.G., Alves, M.A., Almeida, E.C., Carro, L.: Operand size reconfiguration for big data processing in memory. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 710–715. IEEE (2017)

    Google Scholar 

  22. Santos, P.C., et al.: Exploring iot platform with technologically agnostic processing-in-memory framework. In: Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, pp. 1–6 (2018)

    Google Scholar 

  23. Scrbak, M., Islam, M., Kavi, K.M., Ignatowski, M., Jayasena, N.: Exploring the processing-in-memory design space. J. Syst. Architect. 75, 59–67 (2017)

    Article  Google Scholar 

  24. Venners, B.: The java virtual machine. Java and the Java virtual machine: definition, verification, validation (1998)

    Google Scholar 

  25. Wang, Q., Wang, X., Lee, S.H., Meng, F.H., Lu, W.D.: A deep neural network accelerator based on tiled rram architecture. In: 2019 IEEE International Electron Devices Meeting (IEDM), pp. 14–4. IEEE (2019)

    Google Scholar 

  26. Zhang, D., Jayasena, N., Lyashevsky, A., Greathouse, J.L., Xu, L., Ignatowski, M.: Top-pim: Throughput-oriented programmable processing in memory. In: Proceedings of the 23rd International Symposium on High-performance Parallel and Distributed Computing, pp. 85–98 (2014)

    Google Scholar 

  27. Zhuo, Y., et al.: Graphq: Scalable pim-based graph processing. In: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 712–725 (2019)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Rafael Fão de Moura .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2023 IFIP International Federation for Information Processing

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Moura, R.F.d., Carro, L. (2023). Exploiting Heterogeneity in PIM Architectures for Data-Intensive Applications. In: Henkler, S., Kreutz, M., Wehrmeister, M.A., Götz, M., Rettberg, A. (eds) Designing Modern Embedded Systems: Software, Hardware, and Applications. IESS 2022. IFIP Advances in Information and Communication Technology, vol 669. Springer, Cham. https://doi.org/10.1007/978-3-031-34214-1_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-031-34214-1_5

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-34213-4

  • Online ISBN: 978-3-031-34214-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics