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Analysis of a Network Interface for an On-Chip Network Architecture

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Intelligent Technologies: Design and Applications for Society (CITIS 2022)

Part of the book series: Lecture Notes in Networks and Systems ((LNNS,volume 607))

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Abstract

This document details a study on the Network Interface (Network on Chip), focused on performance parameters, by injecting traffic of diverse types, CBR traffic and multimedia traffic, which are the most used today. For this, a NIRGAM Network simulator is used as a tool, which has the necessary configuration parameters to obtain the performance, latency, and power values to analyse the proposal. The results show that performance is a parameter that can be optimized by increasing the flit and/or operating frequency value, but without neglecting the power consumption that it would generate.

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Author information

Authors and Affiliations

  1. Universidad de las Fuerzas Armadas ESPE, Sangolquí, Ecuador

    Byron Ojeda, Verónica Alulema & Darwin Alulema

  2. Universidad Politécnica Salesiana, Cuenca, Ecuador

    Mayerly Saenz

Authors
  1. Byron Ojeda
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  2. Mayerly Saenz
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  3. Verónica Alulema
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  4. Darwin Alulema
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Corresponding author

Correspondence to Darwin Alulema .

Editor information

Editors and Affiliations

  1. Campus El Vecino, Universidad Politécnica Salesiana, Cuenca, Ecuador

    Vladimir Robles-Bykbaev

  2. Research Centre on Production Management and Engineering - CIGIP, Universitat Politècnica de València, Alcoy, Spain

    Josefa Mula

  3. Rua Imaculada Conceiçao, Pontifícia Universidade Católica do Paraná – PUCPR, Curitiba, Brazil

    Gilberto Reynoso-Meza

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Ojeda, B., Saenz, M., Alulema, V., Alulema, D. (2023). Analysis of a Network Interface for an On-Chip Network Architecture. In: Robles-Bykbaev, V., Mula, J., Reynoso-Meza, G. (eds) Intelligent Technologies: Design and Applications for Society. CITIS 2022. Lecture Notes in Networks and Systems, vol 607. Springer, Cham. https://doi.org/10.1007/978-3-031-24327-1_7

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