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Level-Up - From Bits to Words

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Formal Methods: Foundations and Applications (SBMF 2022)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 13768))

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Abstract

Model checking based on SAT solving has been successfully applied to hardware and software verification. Most of the time the verification is done on the single bit-level using Boolean logic to represent operations on atomic data types.

With the extension of SAT solving to SMT solving, there exist solvers which can use more abstract reasoning on the word-level. SMT solvers support richer theories and allow for adding additional lemmas that can speed up verification.

In this paper we show how a combination of bit and word-level analysis can speed up the verification of hardware models specified on the word-level. We combine the analysis efficiency of SAT solvers to identify bit-level information that is added to the word-level model. Effectively we use different bit-level invariant generation to augment word-level models. We validate the approach on the HWMCC word-level benchmarks using different integration strategies and state-of-the-art model-checkers.

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Notes

  1. 1.

    http://fmv.jku.at/hwmcc20/.

  2. 2.

    http://fmv.jku.at/hwmcc20/hwmcc20benchmarks.tar.xz.

  3. 3.

    https://github.com/aman-goel/avr.

  4. 4.

    https://github.com/upscale-project/pono.

  5. 5.

    https://upscale.stanford.edu/.

  6. 6.

    https://github.com/boolector/btor2tools.

  7. 7.

    https://github.com/arbrad/IC3ref.

  8. 8.

    https://www.dropbox.com/s/ny9fu0va1bz2zls/extended_models.tar.xz?dl=0.

  9. 9.

    tag HWMCC of https://github.com/aman-goel/avr.

  10. 10.

    8b2a94649f5ea1161260a611de4b49e6f5d92b98 of https://github.com/upscale-project/pono.

References

  1. Barrett, C., Fontaine, P., Tinelli, C.: The SMT-LIB standard: version 2.6. Technical report, Department of Computer Science, The University of Iowa (2017). www.smt-lib.org/

  2. Biere, A.: Tutorial on world-level model checking. In: 2020 Formal Methods in Computer Aided Design (FMCAD) (2020)

    Google Scholar 

  3. Biere, A., Cimatti, A., Clarke, E., Zhu, Y.: Symbolic model checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, pp. 193–207. Springer, Heidelberg (1999). https://doi.org/10.1007/3-540-49059-0_14

    Chapter  Google Scholar 

  4. Biere, A., Claessen, K.: Hardware model checking competition. In: Hardware Verification Workshop (2010)

    Google Scholar 

  5. Biere, A., Heljanko, K., Wieringa, S.: AIGER 1.9 and beyond (2011)

    Google Scholar 

  6. Bjesse, P.: A practical approach to word level model checking of industrial netlists. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 446–458. Springer, Heidelberg (2008). https://doi.org/10.1007/978-3-540-70545-1_43

    Chapter  Google Scholar 

  7. Bjesse, P.: Word-level sequential memory abstraction for model checking. In: 2008 Formal Methods in Computer-Aided Design (2008)

    Google Scholar 

  8. Bjesse, P.: Word-level bitwidth reduction for unbounded hardware model checking. Formal Methods Syst. Des. 35(1), 56–72 (2009). https://doi.org/10.1007/s10703-009-0080-2

    Article  MATH  Google Scholar 

  9. Bjesse, P., Claessen, K.: SAT-based verification without state space traversal. In: Hunt, W.A., Johnson, S.D. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 409–426. Springer, Heidelberg (2000). https://doi.org/10.1007/3-540-40922-X_23

    Chapter  Google Scholar 

  10. Bradley, A.R.: SAT-based model checking without unrolling. In: Jhala, R., Schmidt, D. (eds.) VMCAI 2011. LNCS, vol. 6538, pp. 70–87. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-18275-4_7

    Chapter  Google Scholar 

  11. Breton, N., Fonteneau, Y.: S3: proving the safety of critical systems. In: Lecomte, T., Pinger, R., Romanovsky, A. (eds.) RSSRail 2016. LNCS, vol. 9707, pp. 231–242. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-33951-1_17

    Chapter  Google Scholar 

  12. Champion, A., Mebsout, A., Sticksel, C., Tinelli, C.: The Kind 2 model checker. In: Chaudhuri, S., Farzan, A. (eds.) CAV 2016. LNCS, vol. 9780, pp. 510–517. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-41540-6_29

    Chapter  Google Scholar 

  13. Cimatti, A., Griggio, A.: Software model checking via IC3. In: Madhusudan, P., Seshia, S.A. (eds.) CAV 2012. LNCS, vol. 7358, pp. 277–293. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-31424-7_23

    Chapter  Google Scholar 

  14. Gacek, A., Backes, J., Whalen, M., Wagner, L., Ghassabani, E.: The JKind model checker. In: Chockler, H., Weissenbacher, G. (eds.) CAV 2018. LNCS, vol. 10982, pp. 20–27. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-96142-2_3

    Chapter  Google Scholar 

  15. Goel, A., Sakallah, K.: Model checking of Verilog RTL using IC3 with syntax-guided abstraction. In: Badger, J.M., Rozier, K.Y. (eds.) NFM 2019. LNCS, vol. 11460, pp. 166–185. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-20652-9_11

    Chapter  Google Scholar 

  16. Gurfinkel, A., Belov, A., Marques-Silva, J.: Synthesizing safe bit-precise invariants. In: Ábrahám, E., Havelund, K. (eds.) TACAS 2014. LNCS, vol. 8413, pp. 93–108. Springer, Heidelberg (2014). https://doi.org/10.1007/978-3-642-54862-8_7

    Chapter  Google Scholar 

  17. Gurfinkel, A., Ivrii, A.: K-induction without unrolling. In: FMCAD (2017)

    Google Scholar 

  18. Jahier, E., Raymond, P., Halbwachs, N.: The lustre V6 reference manual. Verimag, Grenoble (2016)

    Google Scholar 

  19. Jovanović, D., Dutertre, B.: Property-directed K-induction. In: 2016 Formal Methods in Computer-Aided Design (FMCAD), pp. 85–92 (2016)

    Google Scholar 

  20. Khasidashvili, Z., Nadel, A.: Implicative simultaneous satisfiability and applications. In: Eder, K., Lourenço, J., Shehory, O. (eds.) HVC 2011. LNCS, vol. 7261, pp. 66–79. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-34188-5_9

    Chapter  Google Scholar 

  21. Mann, M., et al.: Pono: a flexible and extensible SMT-based model checker. In: Silva, A., Leino, K.R.M. (eds.) CAV 2021. LNCS, vol. 12760, pp. 461–474. Springer, Cham (2021). https://doi.org/10.1007/978-3-030-81688-9_22

    Chapter  Google Scholar 

  22. Mattarei, C., Mann, M., Barrett, C., Daly, R.G., Huff, D., Hanrahan, P.: CoSA: integrated verification for agile hardware design. In: Formal Methods in Computer-Aided Design, FMCAD 2018, Austin, Texas, USA, 30 October–2 November 2018. IEEE (2018)

    Google Scholar 

  23. Niemetz, A., Preiner, M., Wolf, C., Biere, A.: Btor2, BtorMC and Boolector 3.0. In: Chockler, H., Weissenbacher, G. (eds.) CAV 2018. LNCS, vol. 10981, pp. 587–595. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-96145-3_32

    Chapter  Google Scholar 

  24. Ordioni, J., Breton, N., Colaço, J.L.: HLL v. 2.7 modelling language specification (2018)

    Google Scholar 

  25. Sheeran, M., Singh, S., Stålmarck, G.: Checking safety properties using induction and a SAT-solver. In: Hunt, W.A., Johnson, S.D. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 127–144. Springer, Heidelberg (2000). https://doi.org/10.1007/3-540-40922-X_8

    Chapter  Google Scholar 

  26. Sheeran, M., Stålmarck, G.: A tutorial on stålmarck’s proof procedure for propositional logic. In: Gopalakrishnan, G., Windley, P. (eds.) FMCAD 1998. LNCS, vol. 1522, pp. 82–99. Springer, Heidelberg (1998). https://doi.org/10.1007/3-540-49519-3_7

    Chapter  Google Scholar 

  27. Tange, O.: GNU parallel 20220322 (2022). https://doi.org/10.5281/zenodo.6377950

  28. Wolf, C., Glaser, J.: Yosys-a free verilog synthesis suite. In: Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip) (2013)

    Google Scholar 

  29. Zhang, H., Gupta, A., Malik, S.: Syntax-guided synthesis for lemma generation in hardware model checking. In: Henglein, F., Shoham, S., Vizel, Y. (eds.) VMCAI 2021. LNCS, vol. 12597, pp. 325–349. Springer, Cham (2021). https://doi.org/10.1007/978-3-030-67067-2_15

    Chapter  Google Scholar 

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Güdemann, M., Riedl, K. (2022). Level-Up - From Bits to Words. In: Lima, L., Molnár, V. (eds) Formal Methods: Foundations and Applications. SBMF 2022. Lecture Notes in Computer Science, vol 13768. Springer, Cham. https://doi.org/10.1007/978-3-031-22476-8_8

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  • DOI: https://doi.org/10.1007/978-3-031-22476-8_8

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