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Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations

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Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing

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Abstract

While ASIC-based hardware platforms provide better application-specific cost–accuracy trade-offs, the diversity of embedded systems deploying machine learning algorithms has risen steadily. Consequently, given their reconfigurability and high performance, FPGA-based hardware platforms are increasingly used for embedded machine learning. However, the low-power designs devised for ASICs, using methods such as precision scaling, approximate computing, and mixed/custom quantization, do not result in proportionate gains when implemented on FPGAs. This lack of proportional gains can be attributed primarily to the lack of optimizations for FPGA’s LUT-based architecture in the ASIC-optimized designs. Consequently, there has been active research on improving the efficacy of low-power methods in FPGA-based systems.

In this chapter, we provide an overview of such FPGA-oriented low-power design methods and delve into the details of selected works that report considerable improvements in this regard. Specifically, we cover custom optimizations for both accurate and approximate multiplier designs and MAC units employing mixed quantization of Posit and fixed-point/integer number representations.

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Notes

  1. 1.

    The total number of recorded fractional bits depends on the deployed bit width of the quantization scheme.

  2. 2.

    The data in Fig. 17 refer to the design with the better metrics among the ToolOpt and non-ToolOpt versions.

  3. 3.

    The best-case latency refers to the latency corresponding to the CPD of the design.

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Authors and Affiliations

  1. Technische Universität Dresden, Dresden, Germany

    Salim Ullah, Siva Satyendra Sahoo & Akash Kumar

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  1. Salim Ullah
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  2. Siva Satyendra Sahoo
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  3. Akash Kumar
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Correspondence to Akash Kumar .

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Editors and Affiliations

  1. Colorado State University, Fort Collins, CO, USA

    Sudeep Pasricha

  2. New York University Abu Dhabi, Abu Dhabi, United Arab Emirates

    Muhammad Shafique

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Ullah, S., Sahoo, S.S., Kumar, A. (2024). Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations. In: Pasricha, S., Shafique, M. (eds) Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing. Springer, Cham. https://doi.org/10.1007/978-3-031-19568-6_4

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  • DOI: https://doi.org/10.1007/978-3-031-19568-6_4

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