Abstract
High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems requiring complex and high-performance closed-loop control strategies for efficient power and thermal management. To satisfy high-bandwidth, real-time multi-input multi-output (MIMO) optimal power control requirements, high-end processors integrate on-die Power Controller Systems (PCS). Traditional PCS is based on a simple microcontroller core supported by dedicated interface logic and sequencers. More scalable and flexible PCS architectures are required to support advanced MIMO control algorithms required for managing the ever-increasing number of cores, power states, and process, voltage, temperature (PVT) variability.
In this paper, we present ControlPULP, a complete, open-source HW/SW RISC-V parallel PCS platform consisting of a single-core microcontroller coupled with a scalable multi-core cluster system with a specialized DMA engine and a fast multi-core interrupt controller for parallel acceleration of real-time power management policies. ControlPULP relies on a real-time OS (FreeRTOS) to schedule a Power Control Firmware (PCF) software layer. We evaluate ControlPULP design choices in a cycle-accurate, event-based simulation environment and show the benefits of the proposed multi-core acceleration solution. We demonstrate ControlPULP in a PCS use-case targeting a next-generation 72-cores HPC processor. We show that the multi-core cluster accelerates the PCF achieving 4.9x speedup with respect to single-core execution.
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Notes
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This has to be considered a first approximation, since it compares post-synthesis results with publicly available data of a modern HPC die, nowadays manufactured in a more advanced technology node.
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In order to assess the controller, the evaluation of a real workload is out of scope for this work as it requires more complex co-simulation setup. We refer to synthetic workloads that cover relevant corner cases for the ControlPULP.
References
AMD: Epyc 7003 Milan (2021). https://en.wikichip.org/wiki/amd/epyc
ARM Ltd.: Arm System Control and Management Interface v3.0. https://developer.arm.com/documentation/den0056/latest
Bambini, G., et al.: An open-source scalable thermal and power controller for HPC processors. In: 2020 IEEE 38th International Conference on Computer Design (ICCD), pp. 364–367 (2020)
Burd, T., et al.: “zeppelin": an soc for multichip architectures. IEEE J. Solid-State Circ. 54(1), 133–143 (2019). https://doi.org/10.1109/JSSC.2018.2873584
Cesarini, D., Bartolini, A., Bonfa, P., Cavazzoni, C., Benini, L.: Countdown: a run-time library for performance-neutral energy saving in MPI applications. IEEE Trans. Comput. 70, 682–695 (2020)
Group, T.L.: Sipearl develops arm hpc chip (2020). https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6227 &year=2020 &tag=3
Gunther, S., Deval, A., Burton, T., Kumar, R.: Energy-efficient computing: power management system on the nehalem family of processors. Intel Technol. J. 14(3), 50–66 (2010)
Intel: Alder Lake (2021). https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake#Codenames
Labs, A.: AWS Graviton 2 (2020). https://en.wikichip.org/wiki/annapurna_labs/alpine/alc12b00
Leiserson, C.E., et al.: There’s plenty of room at the top: what will drive computer performance after Moore’s law? Science 368(6495) (2020)
Liu, Z., Zhu, H.: A survey of the research on power management techniques for high-performance systems. Softw. Pract. Expert 40, 943–964 (2010). https://doi.org/10.1002/spe.v40:11
LLC, G.: Power management for multiple processor cores (US Patent US8402290B2) (2020)
Ltd., A.: System control processor firmware. https://developer.arm.com/tools-and-software/open-source-software/ firmware/scp-firmware
Ltd., A.: Power and Performance Management using Arm SCMI Specification. Technical report (2019)
Montagna, F., et al.: A low-power transprecision floating-point cluster for efficient near-sensor data analytics. IEEE Trans. Parallel Distrib. Syst. 33(5), 1038–1053 (2022). https://doi.org/10.1109/TPDS.2021.3101764
Ripoll, I., Ballester, R.: Period selection for minimal hyper-period in real-time systems (2014)
RISC-V: RISC-V Platform Level Interrupt Controller. https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc
Rosedahl, T., Broyles, M., Lefurgy, C., Christensen, B., Feng, W.: Power/performance controlling techniques in OpenPOWER. In: Kunkel, J.M., Yokota, R., Taufer, M., Shalf, J. (eds.) ISC High Performance 2017. LNCS, vol. 10524, pp. 275–289. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-67630-2_21
Rossi, D., et al.: PULP: a parallel ultra low power platform for next generation IoT applications. In: 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1–39 (2015)
Rossi, D., Loi, I., Haugou, G., Benini, L.: Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters. In: Proceedings of the 11th ACM Conference on Computing Frontiers, CF 2014. Association for Computing Machinery, New York (2014)
Rotem, E., Naveh, A., Ananthakrishnan, A., Weissmann, E., Rajwan, D.: Power-management architecture of the intel microarchitecture code-named sandy bridge. IEEE Micro 32(2), 20–27 (2012). https://doi.org/10.1109/MM.2012.12
Schöne, R., Ilsche, T., Bielert, M., Gocht, A., Hackenberg, D.: Energy efficiency features of the intel skylake-sp processor and their impact on performance. In: 2019 International Conference on High Performance Computing Simulation (HPCS), pp. 399–406 (2019)
Acknowledgment
The study has been conducted in the context of EU H2020-JTI-EuroHPC-2019-1 project REGALE (g.n. 956560), EuroHPC EU PILOT project (g.a. 101034126), EU Pilot for exascale EuroHPC EUPEX (g. a. 101033975), and European Processor Initiative (EPI) SGA2 (g.a. 101036168).
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Ottaviano, A. et al. (2022). ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration. In: Orailoglu, A., Reichenbach, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2022. Lecture Notes in Computer Science, vol 13511. Springer, Cham. https://doi.org/10.1007/978-3-031-15074-6_8
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