Abstract
Design quality of results (QoR) spans metrics of design process outcomes, such as power, performance, area, or runtime, at all stages of the design process. Prediction of design QoR enables efficient searching of the solution space for design, through pruning of unpromising design paths. Without forward-looking predictions, outcomes can only be anticipated constructively, i.e., by running tools. Additionally, a predictor of outcomes for a given stage of design optimization can inform the optimization objectives at earlier, higher-level stages. This chapter gives an overview of machine learning (ML)-based design QoR modeling and prediction: its scope and challenges, key methods, and example application contexts. Generic uses of ML in QoR prediction include shifting the cost vs. accuracy trade-off that is inherent to estimating performance or other design process outcomes, “seeing ahead” to enable early design space exploration and doomed-run filtering, and providing learning and autotuning within multistage design optimizations. At the same time, challenges for ML-based QoR prediction include limitations on data and infrastructure, noise in design tool or flow outcomes in regimes of interest, and difficulty in formulating useful and actionable predictions.
Keywords
- Design QoR prediction
- Prediction challenge
- ML in EDA
- Timing estimation
- Design space exploration
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References
Agnesina, A., Chang, K., Lim, S.K.: VLSI placement parameter optimization using deep reinforcement learning. In: Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1–9 (2020)
Agnesina, A., Pentapati, S., Lim, S.K.: A general framework for VLSI tool parameter optimization with deep reinforcement learning. In: Proceedings of the International Conference on Neural Information Processing Systems (NeurIPS) (2021)
Ba, J.L., Kiros, J.R., Hinton, G.E.: Layer normalization (2016).Preprint. arXiv:1607.06450
Barboza, E.C., Shukla, N., Chen, Y., Hu, J.: Machine learning-based pre-routing timing prediction with reduced pessimism. In: Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 1–6 (2019)
Breiman, L.: Random forests. In: Machine Learning, pp. 5–32 (2001)
Bron, C., Kerbosch, J.: Algorithm 457: finding all cliques of an undirected graph. Commun. ACM 16(9), 575–577 (1973)
Cao, P., Bao, W., Wang, K., Yang, T.: A timing prediction framework for wide voltage design with data augmentation strategy. In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 291–296 (2021)
Chan, W.-T.J., Chung, K.-Y., Kahng, A.B., MacDonald, n.d., Nath, S.: Learning-based prediction of embedded memory timing failures during initial floorplan design. In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 178–185 (2016)
Chan, T.-B., Kahng, A.B., Woo, M.: Revisiting inherent noise floors for interconnect prediction. In: Proceedings of the ACM/IEEE International Workshop on System-Level Interconnect Problems and Pathfinding, pp. 1–7 (2020)
Chen, J., Jiang, I.H.-R., Jung, J., Kahng, A.B., Kim, S., et al.: DATC RDF-2021: design flow and beyond. In: Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 1–6 (2021)
Colizza, V., Flammini, A., Serrano, M.A., Vespignani, A.: Detecting rich-club ordering in complex networks. Nat. Phys. 2, 110–115 (2006)
Coudert, O.: Exact coloring of real-life graphs is easy. In: Proceedings of the Design Automation Conference (DAC), pp. 121–126 (1997)
Esmaeilzadeh, H., Ghodrati, S., Gu, J., Guo, S., Kahng, A.B., et al.: VeriGOOD-ML: an open-source flow for automated ML hardware synthesis. In: Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 1–7 (2021)
Fenstermaker, S., George, D., Kahng, A.B., Mantik, S., Thielges, B.: METRICS: a system architecture for design process optimization. In: Proceedings of the Design Automation Conference (DAC), pp. 705–710 (2000)
Geng, H., Chen, T., Sun, Q., Yu, B.: Techniques for CAD tool parameter auto-tuning in physical synthesis: a survey (invited paper). In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 635-640 (2022)
Grodstein, J., Lehman, E., Harkness, H., Grundmann, B., Watanabe, Y.: A delay model for logic synthesis of continuously-sized networks. In: Proceedings of the IEEE International Conference on Computer Aided Design, pp. 458-462 (1995)
Hamilton, W., Ying, Z., Leskovec, J.: Inductive representation learning on large graphs. In: Proceedings of the International Conference and Workshop on Neural Information Processing Systems (NeurIPS), pp. 1024–1034 (2017)
He, Z., Zhang, L., Liao, P., Ma, Y., Yu, B.: Reinforcement learning driven physical synthesis (invited paper). In: Proceedings of the IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT), pp. 1–4 (2020)
Hill, D., Kahng, A.B.: Guest editors’ introduction: RTL to GDSII – from foilware to standard practice. IEEE Desig. Test Comput. 21(1), 9–12 (2004)
Hochreiter, S., Schmidhuber, J.: Long short-term memory. Neural Comput. 9(8), 1735–1780 (1997)
Hosny, A., Hashemi, S., Shalan, M., Reda, S.: DRiLLS: deep reinforcement learning for logic synthesis. In: Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 581–586 (2020)
Hu, Y., Mettler, M., Mueller-Gritschneder, D., Wild, T., Herkersdorf, A., Schlichtmann, U.: Machine learning approaches for efficient design space exploration of application-specific NoCs. ACM Trans. Desig. Auto. Electron. Syst. 25(5), 1–27 (2020)
International technology roadmap for semiconductors. http://www.itrs2.net/itrs-reports.html
International technology roadmap for semiconductors 2009 design chapter. https://www.dropbox.com/sh/ia1jkem3v708hx1/AAB1fo1HrYIKClJNk0dB7YrCa?dl=0&preview=Design.pdf
Jeong, K., Kahng, A.B.: Methodology from chaos in IC implementation. In: Proceedings of the International Symposium on Quality Electronic Design, pp. 885–892 (2010)
Jung, J., Kahng, A.B., Kim, S., Varadarajan, R.: METRICS2.1 and flow tuning in the IEEE CEDA robust design flow and OpenROAD. In: Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 1–9 (2021)
Kaggle: your machine learning and data science community. https://www.kaggle.com
Kahng, A.B.: Classical floorplanning harmful? In: Proceedings of the International Symposium on Physical Design (ISPD), pp. 207–213 (2000)
Kahng, A.B.: The ITRS design technology and system drivers roadmap: process and status. In: Proceedings of the Design Automation Conference (DAC), pp. 1–6 (2013)
Kahng, A.B.: Open-source EDA: if we build it, who will come? In: Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1–6 (2020)
Kahng, A.B., Mantik, S.: A system for automatic recording and prediction of design quality metrics. In: Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 81–86 (2001)
Kahng, A.B., Mantik, S.: Measurement of inherent noise in EDA tools. In: Proceedings of the International Symposium on Quality Electronic Design, pp. 206–211 (2002)
Kahng, A.B., Li, B., Peh, L.-S., Samadi, K.: ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 423-428 (2009)
Kipf, T.N., Welling, M.: Semi-supervised classification with graph convolutional networks (2016). Preprint. arXiv:1609.02907
Lasse, E., Hubert, S., Remi, M., Karen, S., Volodymir, M., et al.: IMPALA: scalable distributed deep-RL with importance weighted actor-learner architectures. In: Proceedings of the International Conference on Machine Learning (ICML), pp. 1406–1415 (2018)
Lopera, D.S., Servadei, L., Kiprit, G.N., Hazra, S., Wille, R., Ecker, W.: A survey of graph neural networks for electronic design automation. In: Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp. 1–6 (2021)
Lu, Y.-C., Nath, S., Khandelwal, V., Lim, S.K.: Doomed run prediction in physical design by exploiting sequential flow and graph learning. In: Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1–9 (2021)
Luong, T., Pham, H., Manning, C.D.: Effective approaches to attention-based neural machine translation. In: Proceedings of the Conference on Empirical Methods in Natural Language Processing, pp. 1412–1421 (2015)
Ma, Y., He, Z., Li, W., Zhang, L., Yu, B.: Understanding graphs in EDA: from shallow to deep learning. In: Proceedings of the International Symposium on Physical Design (ISPD), pp. 119–126 (2020)
Mnih, V., Kavukcuoglu, K., Silver, D., Graves, A., Antonoglou, I., Wierstra, D., et al.: Playing atari with deep reinforcement learning (2013). Preprint. arXiv 1312.5602
Mnih, V., Badia, A.P., Mirza, M., Graves, A., Lillicrap, T., Harley, T., Silver, D., Kavukcuoglu, K.: Asynchronous methods for deep reinforcement learning. In: Proceedings of the International Conference on Machine Learning (PMLR), pp. 1928–1937 (2016)
Neto, W.L., Austin, M., Temple, S., Amaru, L., Tang, X., Gaillardon, P.-E.: LSOracle: a logic synthesis framework driven by artificial intelligence: invited paper. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–6 (2019)
Sutton, R.S., McAllester, D., Singh, S., Mansour, Y.: Policy gradient methods for reinforcement learning with function approximation. In: Proceedings of the International Conference on Neural Information Processing Systems (NeurIPS), pp. 1057–1063 (1999)
SweRV RISC-V CoreTM 1.1 from western digital. https://github.com/westerndigitalcorporation/swerv_eh1
Tarjan, R.: Depth-first search and linear graph algorithms. In: Proceedings of the Annual Symposium on Switching and Automata Theory (SWAT), pp. 114–121 (1971)
Understanding LSTM networks. https://colah.github.io/posts/2015-08-Understanding-LSTMs/
Veličković, P., Cucurull, G., Casanova, A., Romero, A., Liò, P., Bengio, Y.: Graph attention networks (2017). Preprint. arXiv:1710.10903
Wang, H., Wang, K., Yang, J., Shen, L., Sun, N., Lee, H.-S., Han, S.: GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning. In: Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 1–6 (2020)
Watts, D.J., Strogatz, S.H.: Collective dynamics of ‘small-world’ networks. Nature 393(4), 440–442 (1998)
XGBoost. https://xgboost.readthedocs.io/en/stable/python/python_intro.html
Ziegler, M.M., Liu, H.-Y., Gristede, G., Owens, B., Nigaglioni, R., Carloni, L.P.: A synthesis-parameter tuning system for autonomous design-space exploration. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1148–1151 (2016)
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Kahng, A.B., Wang, Z. (2022). ML for Design QoR Prediction. In: Ren, H., Hu, J. (eds) Machine Learning Applications in Electronic Design Automation. Springer, Cham. https://doi.org/10.1007/978-3-031-13074-8_1
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