Skip to main content
SpringerLink
Log in

Machine Learning for Analog Circuit Sizing

  • Chapter
  • First Online:
Machine Learning Applications in Electronic Design Automation

Abstract

Analog integrated circuit (IC) design is a labor-intensive process amid the lack of automation tools. Sizing of devices, as a key step in analog circuit synthesis, raises many research interests recently, because of both the industrial needs and the advance in machine learning (ML)-inspired algorithms. This chapter first introduces and formulates the analog circuit sizing problem. A brief overview on conventional analog circuit sizing algorithms is also presented. We then review and analyze several recently proposed methods on analog sizing, highlighting the adoption of ML techniques. Finally, we summarize the challenges and opportunities in applying ML for analog circuit sizing problem.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 119.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Alpaydin, G., Balkir, S., Dundar, G.: An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7(3), 240–252 (2003)

    Article  Google Scholar 

  2. Budak, A., Gandara, M., Shi, W., Pan, D., Sun, N., Liu, B.: An efficient analog circuit sizing method based on machine learning assisted global optimization. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. pp. 1–1 (2021). https://doi.org/10.1109/TCAD.2021.3081405

  3. Budak, A.F., Bhansali, P., Liu, B., Sun, N., Pan, D.Z., Kashyap, C.V.: DNN-Opt an RL inspired optimization for analog circuit sizing using deep neural networks. In: Proceedings of the 58th ACM/EDAC/IEEE Design Automation Conference, DAC ’21 (2021)

    Google Scholar 

  4. Chang, E., Han, J., Bae, W., Wang, Z., Narevsky, N., NikoliC, B., Alon, E.: BAG2: a process-portable framework for generator-based AMS circuit design. In: IEEE Custom Integrated Circuits Conference (CICC), pp. 1–8 (2018)

    Google Scholar 

  5. Desautels, T., Krause, A., Burdick, J.W.: Parallelizing exploration-exploitation tradeoffs in gaussian process bandit optimization. J. Mach. Learn. Res. 15(1), 3873–3923 (2014)

    MathSciNet  MATH  Google Scholar 

  6. Fan, S., Cao, N., Zhang, S., Li, J., Guo, X., Zhang, X.: From specification to topology: automatic power converter design via reinforcement learning. In: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–9 (2021)

    Google Scholar 

  7. Frazier, P., Powell, W., Dayanik, S.: The knowledge-gradient policy for correlated normal beliefs. INFORMS J. Comput. 21(4), 599–613 (2009)

    Article  MathSciNet  MATH  Google Scholar 

  8. Gardner, J.R., Kusner, M.J., Xu, Z., Weinberger, K.Q., Cunningham, J.P.: Bayesian optimization with inequality constraints. In: International Conference on Machine Learning (ICML), pp. II-937–II-945 (2014)

    Google Scholar 

  9. Gelbart, M.A., Snoek, J., Adams, R.P.: Bayesian optimization with unknown constraints (2014). arXiv preprint arXiv:1403.5607

    Google Scholar 

  10. Gielen, G., Walscharts, H., Sansen, W.: Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J. Solid-State Circuits 25(3), 707–713 (1990). https://doi.org/10.1109/4.102664

    Article  Google Scholar 

  11. Hakhamaneshi, K., Werblun, N., Abbeel, P., Stojanović, V.: Bagnet: berkeley analog generator with layout optimizer boosted with deep neural networks. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2019). https://doi.org/10.1109/ICCAD45719.2019.8942062

  12. Hennig, P., Schuler, C.J.: Entropy search for information-efficient global optimization. J. Mach. Learn. Res. 13(1), 1809–1837 (2012)

    MathSciNet  MATH  Google Scholar 

  13. Hernández-Lobato, J.M., Hoffman, M.W., Ghahramani, Z.: Predictive entropy search for efficient global optimization of black-box functions. In: Advances in Neural Information Processing Systems, pp. 918–926 (2014)

    Google Scholar 

  14. Hershenson, M., Boyd, S., Lee, T.: Optimal design of a CMOS op-amp via geometric programming. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 20(1), 1–21 (2001). https://doi.org/10.1109/43.905671

    Article  Google Scholar 

  15. Hoffman, M.D., Brochu, E., de Freitas, N.: Portfolio allocation for Bayesian optimization. In: UAI, pp. 327–336. Citeseer (2011)

    Google Scholar 

  16. Hu, H., Li, P., Huang, J.Z.: Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage. In: Proceedings of the International Conference on Computer-Aided Design, pp. 1–8 (2018)

    Google Scholar 

  17. Kennedy, J., Eberhart, R.: Particle swarm optimization. In: Proceedings of ICNN’95—International Conference on Neural Networks, vol. 4, pp. 1942–1948 (1995). https://doi.org/10.1109/ICNN.1995.488968

  18. Koza, J., Bennett, F., Andre, D., Keane, M., Dunlap, F.: Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans. Evol. Comput. 1(2), 109–128 (1997). https://doi.org/10.1109/4235.687879

    Article  Google Scholar 

  19. Kushner, H.J.: A new method of locating the maximum point of an arbitrary multipeak curve in the presence of noise (1964)

    Google Scholar 

  20. Liu, B., Wang, Y., Yu, Z., Liu, L., Li, M., Wang, Z., Lu, J., Fernández, F.V.: Analog circuit optimization system based on hybrid evolutionary algorithms. Integr. VLSI J. 42(2), 137–148 (2009). https://doi.org/10.1016/j.vlsi.2008.04.003

    Article  Google Scholar 

  21. Liu, B., Zhao, D., Reynaert, P., Gielen, G.G.E.: Gaspad: a general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (2014). https://doi.org/10.1109/TCAD.2013.2284109

  22. Liu, M., Turner, W.J., Kokai, G.F., Khailany, B., Pan, D.Z., Ren, H.: Parasitic-aware analog circuit sizing with graph neural networks and Bayesian optimization. In: 2021 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1372–1377 (2021). https://doi.org/10.23919/DATE51398.2021.9474253

  23. Lyu, W., Xue, P., Yang, F., Yan, C., Hong, Z., Zeng, X., Zhou, D.: An efficient Bayesian optimization approach for automated optimization of analog circuits. IEEE Trans. Circuits Syst. I: Regul. Pap. 65(6), 1954–1967 (2017)

    Article  Google Scholar 

  24. Lyu, W., Yang, F., Yan, C., Zhou, D., Zeng, X.: Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design. In: International Conference on Machine Learning, pp. 3312–3320 (2018)

    Google Scholar 

  25. Lyu, W., Yang, F., Yan, C., Zhou, D., Zeng, X.: Multi-objective Bayesian optimization for analog/RF circuit synthesis. In: Proceedings of the 55th Annual Design Automation Conference, pp. 1–6. ACM, New York (2018)

    Google Scholar 

  26. Mockus, J., Tiesis, V., Zilinskas, A.: The application of Bayesian methods for seeking the extremum. Towards Global Optim. 2(117–129), 2 (1978)

    MATH  Google Scholar 

  27. Nye, W., Riley, D., Sangiovanni-Vincentelli, A., Tits, A.: Delight.spice: an optimization-based system for the design of integrated circuits. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 7(4), 501–519 (1988). https://doi.org/10.1109/43.3185

  28. Rasmussen, C.E., Williams, C.K.I.: Gaussian Processes for Machine Learning (Adaptive Computation and Machine Learning. The MIT Press, Cambridge (2005)

    Book  MATH  Google Scholar 

  29. Razavi, B.: Design of Analog CMOS Integrated Circuits, 1 edn. McGraw-Hill, New York (2001)

    Google Scholar 

  30. Ren, H., Kokai, G.F., Turner, W.J., Ku, T.S.: ParaGraph: layout parasitics and device parameter prediction using graph neural networks. In: ACM/IEEE Design Automation Conference (DAC) (2020)

    Google Scholar 

  31. Rutenbar, R.: Analog design automation: Where are we? Where are we going? In: IEEE Custom Integrated Circuits Conference (CICC) (1993). https://doi.org/10.1109/CICC.1993.590704

  32. Schonlau, M., Welch, W.J., Jones, D.R.: Global versus local search in constrained optimization of computer models. Lecture Notes-Monograph Series, pp. 11–25 (1998)

    Google Scholar 

  33. Scott, W., Frazier, P., Powell, W.: The correlated knowledge gradient for simulation optimization of continuous parameters using gaussian process regression. SIAM J. Optim. 21(3), 996–1026 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  34. Settaluri, K., Haj-Ali, A., Huang, Q., Hakhamaneshi, K., Nikolić, B.: Autockt: deep reinforcement learning of analog circuit designs. In: IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE) (2020)

    Google Scholar 

  35. Shahriari, B., Swersky, K., Wang, Z., Adams, R.P., De Freitas, N.: Taking the human out of the loop: a review of Bayesian optimization. Proc. IEEE 104(1), 148–175 (2015)

    Article  Google Scholar 

  36. Shahriari, B., Wang, Z., Hoffman, M.W., Bouchard-Côté, A., de Freitas, N.: An entropy search portfolio for Bayesian optimization (2014). arXiv preprint arXiv:1406.4625

    Google Scholar 

  37. Shook, B., Bhansali, P., Kashyap, C., Amin, C., Joshi, S.: MLParest: machine leaning based parasitic estimation for custom circuit design. In: ACM/IEEE Design Automation Conference (DAC) (2020)

    Google Scholar 

  38. Srinivas, N., Krause, A., Kakade, S.M., Seeger, M.: Gaussian process optimization in the bandit setting: no regret and experimental design (2009). arXiv preprint arXiv:0912.3995

    Google Scholar 

  39. Srinivas, N., Krause, A., Kakade, S.M., Seeger, M.W.: Information-theoretic regret bounds for gaussian process optimization in the bandit setting. IEEE Trans. Inform. Theory 58(5), 3250–3265 (2012)

    Article  MathSciNet  MATH  Google Scholar 

  40. Thompson, W.R.: On the likelihood that one unknown probability exceeds another in view of the evidence of two samples. Biometrika 25(3/4), 285–294 (1933)

    Article  MATH  Google Scholar 

  41. Vural, R.A., Yildirim, T.: Swarm intelligence based sizing methodology for CMOS operational amplifier. In: 2011 IEEE 12th International Symposium on Computational Intelligence and Informatics (CINTI), pp. 525–528 (2011)

    Google Scholar 

  42. Wang, H., Wang, K., Yang, J., Shen, L., Sun, N., Lee, H., Han, S.: GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning. In: ACM/IEEE Design Automation Conference (DAC) (2020)

    Google Scholar 

  43. Wang, Z., Jegelka, S.: Max-value entropy search for efficient Bayesian optimization (2017). arXiv preprint arXiv:1703.01968

    Google Scholar 

  44. Zhang, G., He, H., Katabi, D.: Circuit-GNN: graph neural networks for distributed circuit design. In: Chaudhuri, K., Salakhutdinov, R. (eds.) Proceedings of the 36th International Conference on Machine Learning. Proceedings of Machine Learning Research, vol. 97, pp. 7364–7373. PMLR (2019)

    Google Scholar 

  45. Zhang, S., Lyu, W., Yang, F., Yan, C., Zhou, D., Zeng, X.: Bayesian optimization approach for analog circuit synthesis using neural network. In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1463–1468. IEEE, Piscataway (2019)

    Google Scholar 

  46. Zhang, S., Lyu, W., Yang, F., Yan, C., Zhou, D., Zeng, X., Hu, X.: An efficient multi-fidelity bayesian optimization approach for analog circuit synthesis. In: Proceedings of the 56th Annual Design Automation Conference 2019, p. 64. ACM, New York (2019)

    Google Scholar 

  47. Zhang, S., Yang, F., Zhou, D., Zeng, X.: Bayesian methods for the yield optimization of analog and sram circuits. In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 440–445. IEEE, Piscataway (2020)

    Google Scholar 

  48. Zhang, S., Yang, F., Zhou, D., Zeng, X.: An efficient asynchronous batch Bayesian optimization approach for analog circuit synthesis. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1–6. IEEE, Piscataway (2020)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. The University of Texas at Austin, Austin, TX, USA

    Ahmet F. Budak, Shuhan Zhang, Mingjie Liu, Wei Shi, Keren Zhu & David Z. Pan

Authors
  1. Ahmet F. Budak
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shuhan Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mingjie Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Wei Shi
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Keren Zhu
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. David Z. Pan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ahmet F. Budak .

Editor information

Editors and Affiliations

  1. NVIDIA, Austin, TX, USA

    Haoxing Ren

  2. Texas A&M University, College Station, TX, USA

    Jiang Hu

Rights and permissions

Reprints and permissions

Copyright information

© 2022 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Budak, A.F., Zhang, S., Liu, M., Shi, W., Zhu, K., Pan, D.Z. (2022). Machine Learning for Analog Circuit Sizing. In: Ren, H., Hu, J. (eds) Machine Learning Applications in Electronic Design Automation. Springer, Cham. https://doi.org/10.1007/978-3-031-13074-8_12

Download citation

Publish with us

Policies and ethics

Search

Navigation