Abstract
In today’s fast-changing and demanding semiconductor market, a new arsenal of design automation solutions must be developed to provide ever-so-needed speedups and dramatic advances in the design process. This chapter presents how traditional physical design algorithms and their extensive portfolio of design settings can be replaced or enhanced with machine learning and a data-driven philosophy. Indeed, using powerful machine learning methods can help mitigate the penalties of the suboptimality of classical approximation algorithms and heuristics by resolving long-lasting NP-hard circuit optimization problems.
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References
Lu, Y.C., Pentapati, S., Lim, S.K.: The law of attraction: affinity-aware placement optimization using graph neural networks. In: Proceedings of the 2021 International Symposium on Physical Design, pp. 7–14 (2021)
De Amorim, R.C., Mirkin, B.: Minkowski metric, feature weighting and anomalous cluster initializing in K-Means clustering. Pattern Recognit. 45(3), 1061–1075 (2012)
Alpert, C.J., Kahng, A.B.: Recent directions in netlist partitioning: a survey. Integration 19(1–2), 1–81 (1995)
Van der Maaten, L., Hinton, G.: Visualizing data using t-SNE. J. Mach. Learn. Res. 9(11) (2008)
Hamilton, W.L., Ying, R., Leskovec, J.: December. Inductive representation learning on large graphs. In: Proceedings of the 31st International Conference on Neural Information Processing Systems, pp. 1025–1035 (2017)
Rousseeuw, P.J.: Silhouettes: a graphical aid to the interpretation and validation of cluster analysis. J. Comput. Appl. Math. 20, 53–65 (1987)
Blondel, V.D., Guillaume, J.L., Lambiotte, R., Lefebvre, E.: Fast unfolding of communities in large networks. J. Stat. Mech. Theory Exp. 2008(10), P10008 (2008)
Panth, S., Samadi, K., Du, Y., Lim, S.K.: Shrunk-2-D: a physical design methodology to build commercial-quality monolithic 3-D ICs. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 36(10), 1716–1724 (2017)
Fiduccia, C.M., Mattheyses, R.M.: A linear-time heuristic for improving network partitions. In: 19th Design Automation Conference, pp. 175–181. IEEE, Piscataway (1982)
Lu, Y.C., Pentapati, S.S.K., Zhu, L., Samadi, K., Lim, S.K.: TP-GNN: a graph neural network framework for tier partitioning in monolithic 3D ICs. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1–6. IEEE, Piscataway (2020)
Karger, D.R.: Global min-cuts in RNC, and other ramifications of a simple min-cut algorithm. In: SODA, vol. 93, pp. 21–30 (1993)
Kipf, T.N., Welling, M.: Semi-supervised classification with graph convolutional networks (2016). arXiv preprint arXiv:1609.02907
Lu, Y.C., Nath, S., Pentapati, S.S.K., Lim, S.K.: A fast learning-driven signoff power optimization framework. In: 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–9. IEEE, Piscataway (2020)
Mok, S., Lee, J., Gupta, P.: Discrete sizing for leakage power optimization in physical design: a comparative study. ACM Trans. Design Autom. Electron. Syst. 18(1), 1–11 (2013)
Ning, W.: Strongly NP-hard discrete gate-sizing problems. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 13(8), 1045–1051 (1994)
Abadi, M., Agarwal, A., Barham, P., Brevdo, E., Chen, Z., Citro, C., Corrado, G.S., Davis, A., Dean, J., Devin, M., Ghemawat, S.: Tensorflow: large-scale machine learning on heterogeneous distributed systems (2016). arXiv preprint arXiv:1603.04467
Kingma, D.P., Ba, J.: Adam: a method for stochastic optimization (2014). arXiv preprint arXiv:1412.6980
Ying, R., Bourgeois, D., You, J., Zitnik, M., Leskovec, J.: Gnn explainer: a tool for post-hoc explanation of graph neural networks (2019). arXiv preprint arXiv:1903.03894
Park, H., Park, J., Kim, S., Cho, K., Lho, D., Jeong, S., Park, S., Park, G., Sim, B., Kim, S., Kim, Y.: Deep reinforcement learning-based optimal decoupling capacitor design method for silicon interposer-based 2.5-D/3-D ICs. IEEE Trans. Compon. Packag. Manuf. Technol. 10(3), 467–478 (2020)
Shi, W., Zhou, Y., Sudhakaran, S.: Power delivery network design and modeling for high bandwidth memory (HBM). In: 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging And Systems (EPEPS), pp. 3–6. IEEE, Piscataway (2016)
Fan, J., Drewniak, J.L., Knighten, J.L., Smith, N.W., Orlandi, A., Van Doren, T.P., Hubing, T.H., DuBroff, R.E.: Quantifying SMT decoupling capacitor placement in DC power-bus design for multilayer PCBs. IEEE Trans. Electromagn. Compatibility 43(4), 588–599 (2001)
Kim, K., Hwang, C., Koo, K., Cho, J., Kim, H., Kim, J., Lee, J., Lee, H.D., Park, K.W., Pak, J.S.: Modeling and analysis of a power distribution network in TSV-based 3-D memory IC including P/G TSVs, on-chip decoupling capacitors, and silicon substrate effects. IEEE Trans. Compon. Packag. Manuf. Technol. 2(12), 2057–2070 (2012)
Sutton, R.S., Barto, A.G.: Reinforcement Learning: An Introduction. MIT Press, Cambridge (2018)
Mnih, V., Kavukcuoglu, K., Silver, D., Rusu, A.A., Veness, J., Bellemare, M.G., Graves, A., Riedmiller, M., Fidjeland, A.K., Ostrovski, G., Petersen, S.: Human-level control through deep reinforcement learning. Nature 518(7540), 529–533 (2015)
Koo, K., Luevano, G.R., Wang, T., Özbayat, S., Michalka, T., Drewniak, J.L.: Fast algorithm for minimizing the number of decap in power distribution networks. IEEE Trans. Electromagn. Compatib. 60(3), 725–732 (2017)
Lu, Y.C., Nath, S., Khandelwal, V., Lim, S.K.: Rl-sizer: VLSI gate sizing for timing optimization using deep reinforcement learning. In: 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 733–738. IEEE, Piscataway (2021)
Lillicrap, T.P., Hunt, J.J., Pritzel, A., Heess, N., Erez, T., Tassa, Y., Silver, D., Wierstra, D.: Continuous control with deep reinforcement learning (2015). arXiv preprint arXiv:1509.02971
Kahng, A.B.: New game, new goal posts: a recent history of timing closure. In: 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6. IEEE, Piscataway (2015)
Stefanidis, A., Mangiras, D., Nicopoulos, C., Dimitrakopoulos, G.: Multi-armed bandits for autonomous timing-driven design optimization. In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 17–22. IEEE, Piscataway (2019)
Lattimore, T., Szepesvári, C.: Bandit Algorithms. Cambridge University Press, Cambridge (2020)
Flach, G., Fogaça, M., Monteiro, J., Johann, M., Reis, R.: Rsyn: an extensible physical synthesis framework. In: Proceedings of the 2017 ACM on International Symposium on Physical Design, pp. 33–40 (2017)
Huang, T.W., Wong, M.D.: OpenTimer: a high-performance timing analysis tool. In: 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 895–902. IEEE, Piscataway (2015)
Swaminathan, M., Han, K.J.: Design and Modeling for 3D ICs and Interposers, vol. 2. World Scientific, Singapore (2013)
Park, S.J., Bae, B., Kim, J., Swaminathan, M.: Application of machine learning for optimization of 3-D integrated circuits and systems. IEEE Trans. Very Large Scale Integr. Syst. 25(6), 1856–1865 (2017)
Snoek, J., Larochelle, H., Adams, R.P.: Practical Bayesian optimization of machine learning algorithms. In: Advances in Neural Information Processing Systems, vol. 25 (2012)
Xie, J., Swaminathan, M.: Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and Joule heating effects. IEEE Trans. Compon. Packag. Manuf. Technol. 1(2), 234–246 (2011)
Park, S.J., Natu, N., Swaminathan, M.: Analysis, design, and prototyping of temperature resilient clock distribution networks for 3-D ICs. IEEE Trans. Compon. Packag. Manuf. Technol. 5(11), 1669–1678 (2015)
Park, S.J., Yu, H., Swaminathan, M.: Preliminary application of machine-learning techniques for thermal-electrical parameter optimization in 3-D IC. In: 2016 IEEE International Symposium on Electromagnetic Compatibility (EMC), pp. 402–405. IEEE, Piscataway (2016)
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Agnesina, A., Lu, YC., Lim, S.K. (2022). Circuit Optimization for 2D and 3D ICs with Machine Learning. In: Ren, H., Hu, J. (eds) Machine Learning Applications in Electronic Design Automation. Springer, Cham. https://doi.org/10.1007/978-3-031-13074-8_10
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DOI: https://doi.org/10.1007/978-3-031-13074-8_10
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