Abstract
The most critical bus in a DSP system today is the memory bus where a large amount of ultra-high-speed data is being transferred from the DSP to the physical memory devices and vice versa. The data on this bus are switching very fast. The rise and fall times of the data, memory clocks, and control signals are approaching sub-nanosecond range. These fast transients generate noise, radiation, power supply droops, signal integrity, and memory timing issues. This chapter covers memory sub-system design techniques to minimize the effects of high-speed data propagating.
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Tran, T.T. (2023). Memory Sub-system Design Considerations. In: High-Speed System and Analog Input/Output Design . Springer, Cham. https://doi.org/10.1007/978-3-031-04954-5_9
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DOI: https://doi.org/10.1007/978-3-031-04954-5_9
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Online ISBN: 978-3-031-04954-5
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