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ESOP 2022: Programming Languages and Systems pp 174–203Cite as

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Verified Security for the Morello Capability-enhanced Prototype Arm Architecture

Verified Security for the Morello Capability-enhanced Prototype Arm Architecture

  • Thomas Bauereiss  ORCID: orcid.org/0000-0001-9607-89429,
  • Brian Campbell  ORCID: orcid.org/0000-0001-6941-503410,
  • Thomas Sewell  ORCID: orcid.org/0000-0002-4891-07979,
  • Alasdair Armstrong9,
  • Lawrence Esswood9,
  • Ian Stark10,
  • Graeme Barnes11,
  • Robert N. M. Watson9 &
  • …
  • Peter Sewell9 
  • Conference paper
  • Open Access
  • First Online: 29 March 2022

  • 2298 Accesses

  • 3 Citations

Part of the Lecture Notes in Computer Science book series (LNCS,volume 13240)

Abstract

Memory safety bugs continue to be a major source of security vulnerabilities in our critical infrastructure. The CHERI project has proposed extending conventional architectures with hardware-supported capabilities to enable fine-grained memory protection and scalable compartmentalisation, allowing historically memory-unsafe C and C++ to be adapted to deterministically mitigate large classes of vulnerabilities, while requiring only minor changes to existing system software sources. Arm is currently designing and building Morello, a CHERI-enabled prototype architecture, processor, SoC, and board, extending the high-performance Neoverse N1, to enable industrial evaluation of CHERI and pave the way for potential mass-market adoption. However, for such a major new security-oriented architecture feature, it is important to establish high confidence that it does provide the intended protections, and that cannot be done with conventional engineering techniques.

In this paper we put the Morello architecture on a solid mathematical footing from the outset. We define the fundamental security property that Morello aims to provide, reachable capability monotonicity, and prove that the architecture definition satisfies it. This proof is mechanised in Isabelle/HOL, and applies to a translation of the official Arm specification of the Morello instruction-set architecture (ISA) into Isabelle. The main challenge is handling the complexity and scale of a production architecture: 62,000 lines of specification, translated to 210,000 lines of Isabelle. We do so by factoring the proof via a narrow abstraction capturing essential properties of arbitrary CHERI ISAs, expressed above a monadic intra-instruction semantics. We also develop a model-based test generator, which generates instruction-sequence tests that give good specification coverage, used in early testing of the Morello implementation and in Morello QEMU development, and we use Arm’s internal test suite to validate our model.

This gives us machine-checked mathematical proofs of whole-ISA security properties of a full-scale industry architecture, at design-time. To the best of our knowledge, this is the first demonstration that that is feasible, and it significantly increases confidence in Morello.

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  1. University of Cambridge, Cambridge, UK

    Thomas Bauereiss, Thomas Sewell, Alasdair Armstrong, Lawrence Esswood, Robert N. M. Watson & Peter Sewell

  2. University of Edinburgh, Edinburgh, UK

    Brian Campbell & Ian Stark

  3. Arm Ltd., Cambridge, UK

    Graeme Barnes

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Bauereiss, T. et al. (2022). Verified Security for the Morello Capability-enhanced Prototype Arm Architecture. In: Sergey, I. (eds) Programming Languages and Systems. ESOP 2022. Lecture Notes in Computer Science, vol 13240. Springer, Cham. https://doi.org/10.1007/978-3-030-99336-8_7

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